What ADS7-V2EBZ Input TRIG (J5) Port Specs are?

Hi There,

The voltage levels 0 and 1.8v are mentioned for enabling and disabling data trigger for AD9694 Eval board in the post, respectively. On the other hand, in Xilinx Spartran-7 FPGA data sheet , the high voltage range is mentioned between 1.2v and 3.3v while  within “Quick Start Guid” for ADS7-V2EBZ FPGA of the AD9695 Eval Board, the low voltage range is provided between 0 and 1.5 v.

I appreciate if you can clarify the confusion and provide the specs of the input TRIG port for ADS7-V2EBZ (i.e. Maximum voltage or current).

Thanks,

Ed



typo fixed
[edited by: Edstar at 12:29 AM (GMT 0) on 17 Jul 2019]
  • Hi There,

    Based on the ADS7-V2EBZ schematic, the J5 input feeds the NC7WZ04 IC. As a result, the trigger port specs would be

    • The Vin min and max reported 0 and 5.5v.
    • The V_input_high min is 0.65Vcc (1.17v) and the V_input_low max is 0.35Vcc (0.63).
    • The  Over-voltage Tolerance inputs facilitates 5V to 3V translation.

    Considering the above specs for the TRIG input port (J5), I believe It is safe to apply pulses between 0 and 3.3v to the J5 GPIO port for triggering the AD9696 Eval board through ADS-V2EBZ. Please kindly advise otherwise.

    Thanks,

    Ed