moving clock synthesizer of ad9864 with high temperature

Hello,

Assuming the FREF frequency remains stable over temp than the likely cause is that the PLL is falling out of lock at higher temp.  Referring to figure 41 of the datasheet, the DC voltage across the varactor should remain a few 100 mV above AGND and below VDDC.  At room temperature, the design goal is to have the DC voltage centered around mid-supply to accommodate temperature drift while staying in its linear region.   Note that if the DC voltage is high, the PLL loop is trying to decrease the varactor contribution capacitance which reduced the value of the series Cv,Cosc contribution thus one could try reducing the Cosc by a few pF.  Conversely........it DC voltage is low, the PLL loop is trying to increase the varactor contribution so one could try increasing the Cosc by a few pF.

If PLL stability over temperature  is the issue than one can increase the KVCO of the oscillator such that a lower dc voltage change would be required to support the temperature drift hence preventing the DC voltage across the varactor from railing near AGND or VDDC.  For an RLC tank circuit with the inductor and varactor contributing to the series R...........the Q=1/R*sqrt(L/C) thus decreasing L and increasing C proportionally should decrease the Q while maintain same resonance frequency.

https://toshiba.semicon-storage.com/us/product/diode/rf-diode/detail.1SV228.html

Hello,

Assuming the FREF frequency remains stable over temp than the likely cause is that the PLL is falling out of lock at higher temp.  Referring to figure 41 of the datasheet, the DC voltage across the varactor should remain a few 100 mV above AGND and below VDDC.  At room temperature, the design goal is to have the DC voltage centered around mid-supply to accommodate temperature drift while staying in its linear region.   Note that if the DC voltage is high, the PLL loop is trying to decrease the varactor contribution capacitance which reduced the value of the series Cv,Cosc contribution thus one could try reducing the Cosc by a few pF.  Conversely........it DC voltage is low, the PLL loop is trying to increase the varactor contribution so one could try increasing the Cosc by a few pF.

If PLL stability over temperature  is the issue than one can increase the KVCO of the oscillator such that a lower dc voltage change would be required to support the temperature drift hence preventing the DC voltage across the varactor from railing near AGND or VDDC.  For an RLC tank circuit with the inductor and varactor contributing to the series R...........the Q=1/R*sqrt(L/C) thus decreasing L and increasing C proportionally should decrease the Q while maintain same resonance frequency.

https://toshiba.semicon-storage.com/us/product/diode/rf-diode/detail.1SV228.html