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LTC1407A CLK and CONV Timing

Dear Community,
i am working with the LTC1407A connected via SPI to a STM32F410 microcontroller. My setup currently is this: I generate one clock pulse and after it is finished I generate 32 clock pulses to read the SPI data. Afterwards, there is a brake of ~1000ns till the next CONV arrives. Unfortunately, the SDO stream stays unstable with levels between high and low and staying high or low after one clock period, and the bits keep on changing.
My problem is that I can either receive 32bits or 40 bits with the STM, so either generating 32 or 40 clocks. The datasheet says 32 clocks should be sufficient if t7 is respected. But I am still not sure, does the LTC maybe need 34 clocks in the end?
Also, from the Timing Diagram in the Datasheet it looks like the CONV Pin and the CLK need to be high at the same time. Is that true? Since there is also a specified time T2 that can be as long as 10 000ns. In my project the CONV pin is toggled on and off before the first clock arrives.

I am grateful for any help.

Many regards
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  • I see, thank you very much for your response.
    Unfortunately the SDO is still fluctuating a lot, with the first bits being high while there is 0V on CH0+ and CH0-.
    Another thing that also confuses me, is that SDO stays high(as in the picture) in between two sets of clocks at 32 clocks which doesn't occur if I use 40 clocks.
    Does anyone know if the LTC1407A minds seeing to many clocks?
    For the bit fluctuation I assume it has to be some electrical issue then.


    This is taken at 32bit and 0V on both inputs of CH0.

  • Can you provide your schematic and a photo of your setup?

    Is it possible you have LTC1407A-1? This is a bipolar part and it would produce a waveform like the one shown depending on the device offset.

    If only 32 clocks are provided, SDO will stay at whatever state the LSB was held at until the next conversion is shifted out. However with 40 clocks, after the 32nd clock the ADC will fill the SDO output with zeros.