Triggering the AD9694 Eval Board externally: "Error: Time out while attempting to fill FIFO"

Hi Aarrants,

After making the AD9694 Eval board functional with the Reference Clock,

I externally triggered the J05 port of the ADS-V2EBZ FPGA, as instructed in


I run into the "ADC Data Capture Error: Timed out while attempting to fill FIFO(s)".

Following the recommendation in the above user guide for the error message, I change the pulse repetition from 11 ms up to 100 ms at 50% duty cycle (1 v up to 1.5 v); however, I still receive the same error message.

The screenshots of the ADC Data Capture Setting General, Capture Board and Device Tabs, and the error message can be access through the .zip file below.

Screenshots_VisualAnalog_ADC_Data_20190502 (1).zip

Could you please let me know how I can work around the issue.



Changed the part number referenced in the subject to accurately reflect the subject matter.
[edited by: deljones at 4:02 PM (GMT 0) on 23 Sep 2019]

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