i am using ad9162 with kcu105 board. DAC operatred with sampling rate 5 GSPS with lane rate as 12.5 gb/s.
Went through the datasheet of AD9162, i have attached the ordering explained but there seems to be ambiguity.
The sample 0 to sample 15 as follows
0x0100, 0x1110, 0x2120, 0x3130, 0x4140, 0x5150, 0x6160, 0x7170, 0x8180, 0x9190, 0xA1A0, 0xB1B0, 0xC1C0, 0xD1D0, 0xE1E0, 0xF1F0.
what should be order in which the 256 bits to be send to JESD IP (xilinx, Tdata) ?, please clarify.
After going through various e2e posts we were able to boil down to issue currently we are facing.
1. i am able to test the phy with all the patterns i.e PRBS7,PRBS15 and PRBS31.
2. The following status are achieved.
0x604 -- Boot loader pass
0x092 -- DLL Status pass
0x281 -- Serdes PLL Lock pass
0x470 -- CGS all lanes pass (0xFF)
all of the above reliably working, when we follow the dac configuration as per datasheet.
But the following status we are not getting.
0x471 -- Frame_Sync (0x00)
0x472 -- Good Checksum (0x00)
0x473 -- Initial lane Sync (0x00)
For checksum calc :
scrambling disabled, For mode: 8114, with HD enabled we obtained checksum 0x4A. i.e Register 0x300, Bit 6 = 0 (default)
we got struck at this stage, any input will be helpful.