AD9680:Spurs around sub-harmonics of the sample clock

I am using AD9680 and HMC7044 toghether.

We are seeing spur in the FFT of the ADC output. It appears that the spur is around fs/2. if the fundamental signal into the ADC is at 200 MHz and 1000 MHz is the sampling clock. I am seeing a spur at 300MHz. This appears to come from ( fs/2-Fin).

1)Can you explain how to reduce this spur?

2)which type of clock is better for 1000MHz sampling clock (LVDS or LVPECL) and explain config clock


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