I am using AD9680 and HMC7044 toghether.
We are seeing spur in the FFT of the ADC output. It appears that the spur is around fs/2. if the fundamental signal into the ADC is at 200 MHz and 1000 MHz is the sampling clock. I am seeing a spur at 300MHz. This appears to come from ( fs/2-Fin).
1)Can you explain how to reduce this spur?
2)which type of clock is better for 1000MHz sampling clock (LVDS or LVPECL) and explain config clock
Thanks,
UmeshJ We have a similar setup with the same behavior: Spur at Fs/2 - Fin. Clock chip is the HMC7044 with 1 GHz sampling clock and 3 GHz VCO Clock, ADC the AD9680 chip. Could you provide the solution, that helped the other customer?
eg. Spur[0] -68.262208 dBc @ 200.729370 MHz for Carrier 299.285889 MHz
UmeshJ We have a similar setup with the same behavior: Spur at Fs/2 - Fin. Clock chip is the HMC7044 with 1 GHz sampling clock and 3 GHz VCO Clock, ADC the AD9680 chip. Could you provide the solution, that helped the other customer?
eg. Spur[0] -68.262208 dBc @ 200.729370 MHz for Carrier 299.285889 MHz
