We observed a power anomaly with the AD9257 when accidentally switching off a 40 MHz input clock before programmatically powering down the chip. The current usage jumped from ~300 mA to nearly 750 mA! This happened with any clock speed. However, if we power on the chip before turning on the clock, current usage is minimal. It only jumps if the clock goes on, then off again.
We can of course work around it by making sure we power down the chip before switching clocks, but this behavior was suprising.
Is this expected, and is there a danger to the chip?
Thanks for using AD9257. I agree; your results are surprising.
I do not believe there is risk of damage to the chip but I'll double check with the design group. First I'll try to locate an AD9257 evaluation board and see if I observe the same thing.
I was able to find an AD9257 board. After the part is up-and-running I removed the clock; the supply current dropped from about 240mA down to about 110mA. My results are quite different from what you are seeing.
Is it possible that there is some ringing or other oscillation happening in your clock circuit or board, that is causing inadvertent high frequency clocking? Could you please try shorting the CLK+ and CLK- pins to each other on your board, after you turn off your clock and are seeing high supply current. Does this change what you see?
What do you do when you switch off your clock? Is the source powered down, disconnected, or ??
Oscilloscope tests on the output clocks (frame + data) show they are flat after turning off the input clock. This is a custom built board that outputs into an FPGA (not connected), so many outputs are floating right now.
On our test bench, we use an Agilent signal generator that outputs into a balun (common-mode choke), which then drives the clk +/-. We also use blocking capacitors in series before the chip pins. Switching off the clock is done by toggling the 'RF out' button.
We can try shorting the input clk pins tomorrow.
After removing the clock and observing the current jump, it can be restored/fixed by programming a power mode reset.
Thanks for the information.
When the problem is fixed by a "power mode reset", is this by SPI or by using the PDWN pin?
Also, in addition to shorting the clock input pins, is it possible for you to tie one clock pin high (1.8V) and the other clock pin low? This would be more effective to insure that there is no inadvertent clocking.
The clock circuit on your board sounds very similar to the one on our evaluation board.
The power mode reset/shutdown/run is all done via SPI. We are not using the PDWN pin.
I'm sorry I got to this a bit late. But shorting the clk pins made no difference; however, tying clk- to GND and clk+ to 1.8V did work, current was reduced from ~450 mA to ~190mA (running a test mode). When removing the 1.8V from the clk+ pin, the current would jump back up, but only sometimes - plugging it back in and removing it would also keep the current low about 50% of the time. I was using the same 1.8V line for DVdd, AVdd, and clk+.