I have been trying to be able to use the full 250MSPS capable of the ad9250 and according to the datasheet, this can only be done using 2 lanes? Is this correct?
When I use just one lane ML=11, it works for low frequency signals up to about 40Mhz but I am unable to sample a 70Mhz sine wave correctly. It is very distorted. I guess because the sampling rate is only 125Msps(below nyquist). When I switch to 2 lanes, I can only get it to work if the M is also 2 ( 2 converters). The problem with that is part of the data is from converter A and the other is from converter B. My signal is only going to converter A . I am using the ad9250 -250EBZ eval board.
I think what I need is M=1 and L=2. So I can feed the signal to just one converter but get the full 250MSPS.
Setting it to M=1(1 converter), L=2 (2 lanes) mode doesn’t work, sync signal stays low. I am not sure if I am doing anything wrong. According to table 13 below, the only difference for this mode is to set the HD to ‘1’ in in this mode and I do that in the JESD core I am using, somehow it doesn’t work whether I set it or not.
These are the contents of my ROM file I use to configure the ADC, I think the relevant part is highlighted yellow.
I have used this same file with that part changed to 005E11 and 005E22 and they all work. But as soon as I change it to 005E12, it keeps syncing (sync signal never comes up).
0 : 00003c ; -- reset ADC
1 : 0000DE ; -- wait for 500us command
2 : 005F15 ; -- 0 AD9250 #1, write 0x15 to link control 1 register 0x5F to disable the lane
3 : 006E81 ; -- 1 # write 0x81(enable) or 0x01(to disable) to parameter SCR/L register 0x6E to enable/disable scrambler
4 : 005E12 ; -- 2 AD9250 #1, write ML to quick config register 0x5E for M= number of converters ,L= number of lanes/converter
5 : 00FF01 ; -- 3 AD9250 #1, write 0x01 to device update register 0xFF to update the settings
6 : 00701F ; -- 4 write to parameter K register 0x70 (for K=32, write 0x1F)(for K=16, write 0x0F)
7 : 00FF01 ; -- 5 AD9250 #1, write 0x01 to device update register 0xFF to update the settings
8 : 00730F ; -- 6 AD9250 #1, write 0x0F to parameter subclass/Np register 0x73 for subclass 0
9 : 807500 ; --read high density mode, expect Bit 7 to be high
A : 807100 ; --read M(number of converters) , expect Bit 7:0 to be x01
B : 806E00 ; --read L(number of lanes) , expect Bit 7:0 to be x02
C : 005F14 ; -- 7 AD9250 #1, write 0x14 to link control 1 register 0x5F to enable the lane
[D..F] : FFFFFF ; -- 8 Fin
I have also tried setting register 83 to 0x30 (82 left at default 0x02) so that lane A is routed to both Lane 0 and Lane 1. I'm guessing that's what you need to acheive 250Msps?
Any help will be greatly appreciated.
The JESD204B lane rate is limited to 5 GSPS. As a result, you would need to use two lanes (L=2) such that the lane rate is at 5 GSPS. Note that the default settings (see Table 13 of datasheet) is for two lanes.
Also......the host processor JRx should match the same LMFS configuration and have a coherent reference clock (relative to ADC input 250 MHz clock) used to by the host processors JESD204B PLL such that JESD PLL's on AD9250 and host processor are locked.
hi PMH , thanks for your reply.
Yes, I agree I will have to use 2 lanes to achieve 5 GSPS. My question is do I have to use 1 converter (M =1) to achieve this? ie write 0x12 to the quick config register 0x5E? So the data will be sampled at 250MSPS by one converter and sent on both lanes at a rate of 5Gsps. Do I also need to do any other configurations ? Was considering setting register 0x83 to 0x30 (assign Logical Lane 1 to converter A) as we are only using converter A? Not sure as HD is set in this configuration, this will be done as well.
Any help will be deeply appreciated