Need Help in selection of ADC for CMOS Image Sensor

Question 1 :

I have a CMOS image sensor which gives out analog output as differential

Vcm = 2V and Vdiff is 200mV

But if applied gain at sensor level the Vdiff may go up to 400mV

so the Analog differential voltage operates between 2-400mV to 2+400mV,

My confusion is what is maximum Vpp in ADC selection should i have to consider ? a ADC with Vpp 2.5V ?

Question 2 :

I have HCLK and VCLK for the sensor to be provided, the sensor throws a anlog data out for every falling edge

the maximum limitation of HCLK is 80MHz , i can say my analog sensor samples come out at 80MHz

what should be my sampling rate for these kind of applications, should i need to follow double niquist rate here ? or is there a way i can syncronize the ADC to HCLK and get ADC output for every next rising edge of HCLK

are there any special ADC like these to help me ?

PS: Unfortunately i will not be able to share my datasheet here, upon providing a person mail , i can forward it to you


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