Question 1 :
I have a CMOS image sensor which gives out analog output as differential
Vcm = 2V and Vdiff is 200mV
But if applied gain at sensor level the Vdiff may go up to 400mV
so the Analog differential voltage operates between 2-400mV to 2+400mV,
My confusion is what is maximum Vpp in ADC selection should i have to consider ? a ADC with Vpp 2.5V ?
Question 2 :
I have HCLK and VCLK for the sensor to be provided, the sensor throws a anlog data out for every falling edge
the maximum limitation of HCLK is 80MHz , i can say my analog sensor samples come out at 80MHz
what should be my sampling rate for these kind of applications, should i need to follow double niquist rate here ? or is there a way i can syncronize the ADC to HCLK and get ADC output for every next rising edge of HCLK
are there any special ADC like these to help me ?
PS: Unfortunately i will not be able to share my datasheet here, upon providing a person mail , i can forward it to you
Thank you for posting on EngineerZone.
Reply to Question 1:Because you are stating the input voltage range with respect to VCM, it seems to me that the voltages you describe are single ended. If each single ended signal can swing from 2V-400mV to 2V+400mV (800mVpp single ended), then your differential signal amplitude is 1.6V peak-to-peak differential. If this is correct you will need to use an ADC with input full-scale voltage of greater than 1.6Vpp differential.
The ADCs I am familiar with have an input VCM requirement lower than 2V. You'll need to shift your VCM level down to be compatible with whatever ADC you choose. This is usually done with an amplifier.
Reply to Question 2:The Nyquist rate applies to signal bandwidth. Ideally, if you have an 80MHz bandwidth signal, you'll need to sample at >160MHz to allow for a continuous 80MHz spectrum without aliasing. In reality you'll need an even higher sample rate to allow for realistic anti-aliasing filter roll-off.
You mention a signal frequency of 80MHz. If it is a narrow band signal, you can convert it with a lower sample rate ADC. In this case the analog input bandwidth of the ADC must be greater than 80MHz.
What is the bandwidth of your signal?
No , the sensor output is a differential one, it has two outputs vout+ and vout-, Vcm is 2V and output varies +/- 400mV
if seen as differential input the swing is 400mV
basically the data is an image data from sensor, so i feel the data wont change that fast, i am not sure how fastly an image data changes when read from a cmos through rolling shutter based scan
the sensor company is currently using a adc9245 as ADC and ad8032 as voltage followers between analog output and adc
i want to change the above configuration from 3.3v adc to 1.8v cmos adc, so i have chosen ad9649 as ADC
the datasheet of ad9649 suggests ad8352 as input driver and ad9513 as clock driver , this configuration is power hungry and more in resource for my requirement
so i have chosen ada4807-2 as input driver, for clock driver/jitter cleaner i want to use ltc6957-2
kindly throw your valuable comments on my selection
I'm not an amplifier nor a clocking expert, but here are some comments.
I'm sorry to mention all these issues, but it seems to me that the ADA4807 will be difficult to make work with the AD9649 at your system frequencies.
The ADA4930 is an amplifier that is well matched to low voltage ADCs with differential inputs, but does consume more power.
The LTC6957-2 (LVDS) seems OK to me.
Maybe the amplifier and clock guys will get notified because of the part numbers being mentioned, and can provide additional information.