# AD9287 Dataout frequency not right

I  have gotten a problem with AD9287ABCPZ-100, as follows,

According to the Timing diagram of AD9287 ,when my input  clock is 20Mhz, the frequency of dataout should be 80Mhz ,and the bit clock(DCO) should be 80Mhz ,frame clock(FCO) should be 20Mhz .

But in fact ，the frequency of DCO and DCO is right ,but the frequence of dataout is 20Mhz,too. So it makes me confused ,Idont know which question leads to this. SO I need a help.

Parents
• this is FCO

this is DCO

this is dataout

• Hi Xiawen,

Thank you for using the AD9287.

I agree with what you state from the AD9287 datasheet timing diagram.

Would you please double-check the signals you are probing? I believe it is impossible for FCO frequency to be greater than DCO frequency, and FCO frequency to be the same as the serial data output waveform frequency.

Thank you.

Doug

• Hi Doug,

Yes,I am using differential probes.And this is my PCB, the three differential pairs are all 1673 mils long.

You can see from the picture, I just use D+A, D-A, FCO+, FCO-, DCO+ and DCO-. What I mean is that the other pins ,like D+B, are floating.

Ok, thank you Dougs,  I'm debugging AD9287 to see if FPGA can read the data correctly.

• And，I find that both the differential output  voltage（A digital output and B digital output）are negative value， is it right？

• Hi Xiawen,

A negative differential voltage (voltage on D+A - D-A --> negative) on the LVDS outputs corresponds to a logic 0 value. This sounds like a reasonable static value. I do not know the state of the ADC when you are taking that measurement but logic 0 output does not necessarily indicate any kind of problem.

Doug

• Thank you very much, Doug. I have solved this problem, thanks for your patient reply, best wishes!

• Hi Xiawen,

Great work! Thanks for letting me know.

Can you say a little about what the problem was?

Thank you.

Doug