I have gotten a problem with AD9287ABCPZ-100, as follows,
According to the Timing diagram of AD9287 ,when my input clock is 20Mhz, the frequency of dataout should be 80Mhz ,and the bit clock(DCO) should be 80Mhz ,frame clock(FCO) should be 20Mhz .
But in fact ，the frequency of DCO and DCO is right ,but the frequence of dataout is 20Mhz,too. So it makes me confused ,Idont know which question leads to this. SO I need a help.
Thanks for your answer !
this is FCO
this is DCO
this is dataout
Thank you for using the AD9287.
I agree with what you state from the AD9287 datasheet timing diagram.
Would you please double-check the signals you are probing? I believe it is impossible for FCO frequency to be greater than DCO frequency, and FCO frequency to be the same as the serial data output waveform frequency.
Thanks for your patient reply. In fact ,I check the data signals, then I find that when my analog input is equal to 0, the frequency of data_out is equal to FCO, while even if it is not 0, the frequency of data_ out is higher ,but I can't tell it's eight times the frequency of the FCO. Here is the diagram that analog input is not equal to zero when FCO = 20Mhz.Thank you!
What I said is that my FCO and DCO is right,the FCO diagram I showed is 50ns/div, eqaul to 10 times of DCO.
Sorry, it seems that I misunderstood your question. OK, FCO and DCO frequencies are correct.
Do you have SPI control of your AD9287? If so can you try one of the stored digital test patterns to look at your output data? Sometimes noise can cause one or more of the lower order bits to flip randomly which can make observation of the output frequency more difficult.
For example, to output a checkerboard pattern you would do the following SPI sequence:
Write Register 0x0D = 0x04 #select checkerboard test patternWrite Register 0xFF = 0x01 #transfer bit to put previous SPI writes into effect
Is this something you can try?
This is my first time to design a PCB, so I didn't add SPI communication between FPGA and AD9287.So I can't finish this.. Is there any another way?
Yes, there is another way. If you designed your board for no SPI communication, CSB is tied high, correct?. In that case do you have the ability to tie the SCLK/DTP (pin 28) high or low? When CSB is tied high at ADC power-up, then the SCLK/DTP pin functions as a control bit for outputting a known test pattern.
SCLK/DTP pin low: Normal ADC operationSCLK/DTP pin high (AVDD): shift out 1000 0000 on each channelPlease see the AD9287 datasheet Table 12 for more information.
Do you have the ability to control the voltage on SCLK/DTP?
I just followed your instructions,and these are the waveform I got. Are they right?
The sample frequency is 20Mhz. So the cycle is 50ns, the waveform shows below means 1000,000 ?
The first picture is the waveform of D+A minus D-A, and the second is D+B (-) D-B.
In fact, only the first ADC is used, and the other ADCs' pins are suspended.
So their amplitude are not same ?
Thanks for your reply!
The frequency of the output pulse looks consistent with shifting out 1000 0000, though the waveform does not look good. Looking at your "dataout" oscilloscope screen shot again from your previous post, the waveform looks similar. I missed this before.
Are you using differential probes?How close to the 100Ohm shunt LVDS termination are you probing?Is the 100Ohm shunt LVDS termination close to the receiver?How far from the ADC is your receiver?
Also, what do you mean by "the other ADCs' pins are suspended"? Which pins are "suspended", and what are you doing to suspend the pins?
Yes,I am using differential probes.And this is my PCB, the three differential pairs are all 1673 mils long.
You can see from the picture, I just use D+A, D-A, FCO+, FCO-, DCO+ and DCO-. What I mean is that the other pins ,like D+B, are floating.
Ok, thank you Dougs, I'm debugging AD9287 to see if FPGA can read the data correctly.
And，I find that both the differential output voltage（A digital output and B digital output）are negative value， is it right？
A negative differential voltage (voltage on D+A - D-A --> negative) on the LVDS outputs corresponds to a logic 0 value. This sounds like a reasonable static value. I do not know the state of the ADC when you are taking that measurement but logic 0 output does not necessarily indicate any kind of problem.