Thres's appliation base on HMCAD1511 sigle input channel to implement the 500M sps , the clock from external clock.
This ADC input clock in 500M, and store 8 8bit data according to Fclk in a single channel mode, so as to realize 500M data sampling. Because eight 8bit pieces of data are stored at a time, trig can occur anywhere in the first eight 8bit pieces of data, making it impossible to accurately find the first 8bit piece of data that is synchronized with trig. I would like to consult whether there is a suitable solution for synchronization. Hope your advice. Thanks.