When I configure the AD6688 parameter,Lane rate is 3.125G, M=4, L =4,F = 2, N '=16, sampling rate 1.25GHZ, d=8, refclk = 156.25MHZ.
- The problem is: when using JESD204B subclass1 mode, I find that my SYNC has been pulled down indicating that there is no synchronization.
- I suspected that Sysref was a problem, but I replaced it with JESD204B subclass0 mode and found that SYNC was always low (excluding Sysref).In addition, I read the internal value of JESD204B register of FPGA side through AXI and determined that the problem was that there was no synchronization on SYNC.
- I tested the DSYNC+ voltage of TP200 on the side of AD6688, and found that the voltage was always about 1.1v after downloading bit. Looking at the manual, it felt like the logic level was always high. But the signal I caught by the chipscope on the FPGA side was always low.So please help me see if my judgment is correct.
- If I'm looking in the wrong direction, please help me check the direction SYNC keeps dragging down the problem. Or other test methods, I don't have any ideas here.