I have a design that uses (2) AD9643 and an AD9467 with an Ultrascale+ FPGA. The hdl for AD9467 is still supported, but support for the AD9643 ended with 2016_r1, unfortunately, one version before support for the Ultrascale+ was added. Anyway, since changes were made to the 2016_r2 version of AD9643, I went ahead and tried it, and it mostly works. The DCO calibrates, I receive correct data from all the test modes, but the time-domain data appears to have multiple offsets applied to it that seems to be correlated to the input voltage. This is true for both channels (the same offsets at the same voltages), but the 2 channels do not appear to be cross-correlated. The below image is the captured output data of a 1MHz sinewave at 250MSPS.
1. What's the best way to proceed with porting the AD9643 to work correctly with the Ultrascale+? I see at least 2 potential solutions:
a. Start with the latest supported version (2016_r1) and port it to work with the Ultrascale+? This didn't look too bad if I don't need to use the idelay3's, but at this point I can't guarantee I can get away with not compensating for trace length mismatches.
b. Start with the earliest non-supported version that's compatible with the Ultrascale+ and port it to work correctly with the AD9643.
2. Should I use the latest hdl version for the AD9467, or should I use whatever version I start with for the AD9643?
3. What's the procedure for writing a delay value to the idelay3's? Looking at the hdl, I thought you just write to consecutive registers starting at byte offset 0x800. However, the DCO always calibrated no matter what delay value I wrote to the idelay3's, and reading back the delay values always returned 0.
Any guidance you can provide is greatly appreciated!