Porting the AD9643 to work with the Ultrascale+


I have a design that uses (2) AD9643 and an AD9467 with an Ultrascale+ FPGA. The hdl for AD9467 is still supported, but support for the AD9643 ended with 2016_r1, unfortunately, one version before support for the Ultrascale+ was added. Anyway, since changes were made to the 2016_r2 version of AD9643, I went ahead and tried it, and it mostly works. The DCO calibrates, I receive correct data from all the test modes, but the time-domain data appears to have multiple offsets applied to it that seems to be correlated to the input voltage. This is true for both channels (the same offsets at the same voltages), but the 2 channels do not appear to be cross-correlated. The below image is the captured output data of a 1MHz sinewave at 250MSPS.

1.  What's the best way to proceed with porting the AD9643 to work correctly with the Ultrascale+? I see at least 2 potential solutions:

    a. Start with the latest supported version (2016_r1) and port it to work with the Ultrascale+? This didn't look too bad if I don't need to use the idelay3's, but at this point I can't guarantee I can get away with not compensating for trace length mismatches.

    b. Start with the earliest non-supported version that's compatible with the Ultrascale+ and port it to work correctly with the AD9643.

2. Should I use the latest hdl version for the AD9467, or should I use whatever version I start with for the AD9643?

3. What's the procedure for writing a delay value to the idelay3's? Looking at the hdl, I thought you just write to consecutive registers starting at byte offset 0x800. However, the DCO always calibrated no matter what delay value I wrote to the idelay3's, and reading back the delay values always returned 0.

Any guidance you can provide is greatly appreciated!


  • Hi Eric,

    I consulted with our internal FPGA Code Dev Team and offer the following:

    "First, since they're using their own Virtex-UltraScale+ FPGA board, they should get rid of most of our RTL. They really only need the iddr_lvds_top module, and since there are slight differences between this module on the 2 projects, I would go with the AD9467_ADS7v2 version of the module.

    The error that they're showing in the plot could be timing at the inputs to the iddr_lvds_top module, or it could be at the point where data goes into their memory or comes out of their memory. I'm assuming that the plot is with their hardware and FPGA program. The shift in data looks like it happens every 32 words, with some additional intermittency. It could be shifting from channel to channel, or it could be an error in time if the clock frequency or write enables are wrong. Shifting between channels can happen if the data capture point is wrong (setup or hold violations between DCO and data inputs). They wouldn't be able to detect this with a test pattern if both channels are set to the same or similar patterns.

    My recommendation is to start with the iddr_lvds_top module from the AD9467 and use the same method for both the AD9467 and AD9643. They can use 2 instantiations of the module, one for each part. The main difference between the modules would be at the bottom where the IDDR outputs are arranged into data words. Outside of these modules, they may want to cross one side over so that all data is on a single clock domain. Each instantiation of iddr_lvds_top will have it's own clock domain, due to each part having its own DCO.

    Regarding the IDELAY3, it looks like they're having trouble using the IDELAY3. Since this is in their design, I would just refer them to the Xilinx user guide, UG571. The IDELAY3 section starts on page 168."

    Best Regards,