I am using an AD9208 in two DDC mode. Decimation ratio is set to 2. My fs is equal to 2.5 GHz.
The following registers hold the values for initial configuration:
0x0310 - DDC0 Control = 0x63
---> Should be Real mixer, 6dB Gain, Fs Hz IF Mode, Complex to real, HB1 Filter selection.
0x0311 - DDC0 Input select = 0x00
0x0327 - DDC0 Test enable = 0x00
0x0330 - DDC1 Control = 0x63
0x0331 - DDC1 Input select = 0x00
0x0347 - DDC1 Test enable = 0x00
When I use this configuration my output signal on both DDCs results in a signal with a DC bias. Which I assume would have been eliminated due to the mixing with fs/4 and filtering with HB1.
I changed register 0x0310 to be 0x43 to be in variable IF and changed the DDC to be fs/4. In variable IF mode and fs Hz IF Mode I received the same result and the DC bias was still there. Additionally I tried changing the DC Offset calibration register 0x0701 to 0x86 instead of 0x06 and the results were the same. Being that the DC was still there.
Why does changing the DC Offset Calibration register result in no change? Is there an additional register I need to set to enable this?
Hi mkutz, what is your ADC use case?
Fs = 2.5GHz
# of DDCs = 2
DDC 0 input from Ch.A?
DDC 1 input from Ch.B?
# lanes, L :
# virtual converters, M :
# octets/frame, F :
Here's the current register settings.
DDC 0 input from channel A = 0x00
DDC0 Q Select = Channel A
DDC0 I Select = Channel A
DDC 1 input from channel B - 0x00
DDC0 Q Select = Channel B
DDC0 I Select = Channel B
DDC0 Control = 0x63
Fs Hz IF Mode
HB1 Decimate by 2
DDC1 Control = 0x63
# of Lanes = 8
# virtual converters = 4
# octets/frame = 1
I am trying to achieve an alias protected bandwidth of (fs/2) * 0.8 (1200 MHz). As shown in table 17 of the documentation. Right now I am just varying DDC0 to see if I can change the results.
If you need anything else let me know.
Additional information is we have a 5 GHz input clock, and we are using the internal clock divider to divide by 2 to get an Fs of 2.5 GHz.
When we put it in full bandwidth mode (no DDC channel, just get real data straight from ADC) we see a DC bias in the data of about 155-165 counts in both channels. We still see this DC bias if we enable the DC offset calibration register (Addr 0x0701). When we enable the decimate by 2 on both DDC channels, the HB1 filter is a little too wide to filter out this DC bias. What we see on our output is a real part of the complex output from the DDC has an alternating bias of +DC bias and -DC bias. This is expected behavior from DDC.
Our question is why are we still seeing the DC bias even after we enable the DC offset calibration register? The DC offset calibration says in the documentation it can remove DC with a +/-512 count offset which we are inside of. We are using the Vadatech AMC589 board. They have the analog input AC coupled. We are using the defaults for voltage reference, which should be internal.