I have a question about the ad9250 ramp test signal in Subclass 1 operation. When I pulse SYNC_N low for at least 4 consecutive LMFCs and bit 4 in the 0x3A register is on, the data sheet says that "the internal clock alignment for the JESD204B timing is forced". Does this mean also that the ramp test signal position is also reset to 0? I am asking because I see the test signal ramps of two AD9250s out of sync even though I believe I did trigger such a timing realignment on both ADCs simultaneously (they are both connected to the same SYNC_N and SYSREF signals). Do the test signals realign as well or is it just real samples that realign?
in test mode, the ADC behaves like a normal ADC, but with test patterns being injected in the datapath. the analog-digital conversion cores are disconnected. the test signals on both channels should realign with the SYSREF signal.