I am using AD9643-250 as ADC. The same signal (ex. 1 MHz sine wave of 0.5 V) entered into the ADC, but the output bit of the ADC depends on the sampling rate (240 or 40 MHz).When using 240 MHz sampling rate, the bit value of Vpeak is smaller than when using 40 MHz.The RC network at the front of the ADC input is used by changing C1 to 10 pF by recommending using R1=33, C1=8.2 pF for the 0 to 100 MHz input signal.Can the output bit value vary depending on the sampling rate?
The ADC converts the Differential Voltage applied directly to its ADC inputs. What is the magnitude of the output code variation you are observing between the 40Msps and 240Msps Clock Rates? Are you verifying the differential voltage is constant directly on the ADC inputs during your measurements?
Thank you for your reply.
What is the magnitude of the output code variation you are observing between the 40Msps and 240Msps Clock Rates?
- In case of 0.5V, 1MHz sine wave, if I use 240Msps clock, output code(14bit) is 4681(01_0010_0100_1001b) and 40Msps clock, output code is bigger than 240MHz clock result.
Are you verifying the differential voltage is constant directly on the ADC inputs during your measurements?
- Yes. I verified the constant differential voltage.
Anyway, I bought the AD9643 evaluation board and HSC-ADC-EVAL to verify above problem.
I followed the quick start guide of AD9643.In addition, 1MHz sine wave with 8dBm power was used for ADC input and the clock was 240MHz.The 40MHz clock is made using the divide ratio of the SPI controller SW as 6.The results confirmed the differences as shown.
I think the ~0.2dBFS variations you are observing between 40Msps and 240Msps sampling rates are being influenced by several factors:
1. The AD9643 has a switched cap input architecture so the Analog source must be capable of charging the sampling capacitors and settling within 1/2 Clock cycle. Please see datasheet page 23 and associated App Note AN-742 for more background. Operation at 40Msps allows more time for the sampling caps to settle and is also more tolerant of poor sample CLK jitter/phase noise.
2. The high noise skirt around the fundamental tone, and the unsuppressed harmonic content represented in your 240Msps FFT plots suggest you are likely not using an analog bandpass filter and/or the quality of your Analog/Clock signal sources are not sufficient for optimal analysis of a 14b ADC.
3. The RF baluns installed on the AD9643 EVB Analog Inputs are only rated by the manufacturer for operation from 4.5MHz to 3GHz. Your 1MHz unfiltered Ain tone is likely getting distorted by the low-freq characteristics of this RF balun.
thank you for your reply and sorry for the late reply.
>> I think settling time is the main reason because the variations from 120MHz to 40MHz is similar.
>> This may be another reason, too.
>> The same difference occurred when I entered the 10 MHz signal.