For our design we are using AD9680 eval board integrated with VCU118 board via FMC.
While configuring the same with SPI, most of the times SPI read is zero. And we are observing when we assert read signal during instruction state , sdio line input to FPGA
has some spikes for that period.
Ideally we should have the data out from ADC to FPGA by next clock cycle.
We have checked the same via your data acquisition card received with ADC eval board. But same thing when we are running our SPI engine it is failing.
More over from FPGA it is 4 wire and we have seen there is data buffer on ADC eval board which make 2 single ended IOs as bidirectional port to ADC chip.
Please let us know if we need to take care of thing which we are missing. Do we have any HDL code available to configure the same.