For our design we are using AD9680 eval board integrated with VCU118 board via FMC.
While configuring the same with SPI, most of the times SPI read is zero. And we are observing when we assert read signal during instruction state , sdio line input to FPGA
has some spikes for that period.
Ideally we should have the data out from ADC to FPGA by next clock cycle.
We have checked the same via your data acquisition card received with ADC eval board. But same thing when we are running our SPI engine it is failing.
More over from FPGA it is 4 wire and we have seen there is data buffer on ADC eval board which make 2 single ended IOs as bidirectional port to ADC chip.
Please let us know if we need to take care of thing which we are missing. Do we have any HDL code available to configure the same.
Received files via email.
I am seeing so many files. Can we get readme file or any user guide if you have any please .
The HDL for AD9680 on ADS7-V2 is available here
I am not able to download this file. Please help me for the same
I was able to download by clicking on the link.
No idea may be our firewall system is blocking. Not able to download the zip file. Its says failure.Retry.
Any other way I can get the files. Can you send this via email. Please do the needful. We are stuck in critical phase.
If you are using Chrome, can you copy paste the link in incognito mode and try again? I am not sure if we have another method. i can try to email it to you
emailed the file.
open the "AD9680_ADS7v2.xpr" file in vivado. it is in the vivado folder
I am seeing the top level file has inputs of spi clk, chip select. As per ADC requirement we should be driving the same. Looks like it is saying blackfin will update. is my understanding or analysis is wrong.
not sure. I am not an fpga expert. i can ask and let you know, but we do not provide any active support for our HDL. it is given on an "as-is" basis.