Could You please clear some things for me:
The datasheet for the device stated that the conversion starts at the rising edge of ENC+ signal.
Is the sample-hold internal capacitor fed with input signal during whole high time of ENC signal or for some other fixed time?
Thanks in advance
The sample switches are driven directly from the encode clock. So when the ENC clock is high the switches are open and the sample cap is charged. When the sample switches close then the charge on the sample cap is transfer into the pipeline and the first stage of conversion begins.