How is source clock phase noise profile related to observed phase noise in AD6676 (datasheet fig. 135)?


I'm evaluating clocking solutions for a design where two AD6676's need to be syncrhonized. The "Clock input considerations" section of the datasheet suggests various topologies and it seems like the best solution in terms of performance would be to just use the HMC7044. However, it's not clear to me how the clock source phase noise relates to the results in figure 135 of the datasheet.

I assume that what figure 135 is depicting is the phase noise you would see on your screen if you injected an extremely pure 300 MHz sinewave to an AD6676 clocked at 3200 MHz, then you made 300 captures, took the FFT and averaged them and then normalized the result to the level seen at 300 Mhz, removed the 300 MHz sine and plotted the phase noise tail.

My question is how that relates to what would see in your signal analyzer if you connected the 3200 MHz ADC clock to your signal analyzer and set it to analyze its phase noise profile.

I'm aware that synthesizers intended to be used as local oscillators in RF frequency conversion processes tend to have a phase noise where low close-in phase noise favored by trading off "plateau" noise level, and that for clocking applications and specially for data converters total integrated jitter is more important so the "plateau" phase noise is favored, trading off close-in phase noise, so it looks like the AD6676 does actually benefit from a clock source made for clocking (of the HMC7044 with wide loop bandwidth in the second PLL, where its performance is unmatched as far as I'm aware), but I'd want to get a sense of how the source clock phase noise profile relates to the observed phase noise of the converter so I can evaluate other clocking solutions that might be worse than HMC7044 but still good enough and have extra desired features.



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  • Hello David,

    Data presented in figure 135 used the R&S SMA100A (with low phase noise option) for the signal source as well as clock source (either as reference to PLL or Direct RF clock input.  We did not characterize the SMA100A with phase noise analyzer albeit phase noise plots are available on their datasheet.  Note that R&S has come out with the R&S SMA100B (also with low phase noise option) so it would be interesting to see if the close in phase noise below 400 KHz improves (when using both generators for IF input and direct RF clock) or not.  If could take a closer look to see if an improvement could be made by using a lower noise LDO for the clock supply (VDDC).  


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