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Input stage simulation of AD9642

Dear experts

We are designing an ASIC (rather low noise and high BW TIA) which we are interfacing with AD9642 @ 160 MHz for data acquisition and we are comparing the performances of  this setup with the same asic interfaced with a differential buffer (ADA4930) connected to a DSO.

I think that we have respected the PCB design rules for the AD9642.

If we compare the noise figures of both setups, we see that we have much more noise with the ADC setup than with the analog buffer.

We suspect a bad coupling between the output stage of the ASIC an the input stage of the ADC.

To try to sort out this problem and hopefully understand it, it would be good to enter the input stage of the ADC in the simulation bench of the ASIC (cadence design tools).

Is there somewhere a description of the input stage of the AD9642, even encrypted, we could use to simulate our full setup ?

Thanks in advance,

best regards