ltc2311-14bits, I can not get how the data out

Hi, I am using the ADC  LTC2311-14 .When I read the datasheet ,it says that the  “Serial Data Output. The conversion result is shifted MSB first on each falling edge of SCK.”  But I read the Timing  Diagram  found that  the last SCK falling edge does not output data or the first SCK falling  edge  and second SCK falling  edge  output the same data- B14 .How do I understand this timing Diagram? Secondly ,the ADC is 14 bit  ,why does it output 15bit data?

  • 0
    •  Analog Employees 
    on Dec 13, 2018 4:09 PM

    SCK of the LTC2311-14 is used for two simultaneous functions, to perform the analog-to-digital conversion and to shift out the result of the previous analog-to-digital conversion. Performing the ADC process requires a total of 16 falling SCK edges. The first two falling edges of SCK after CNV goes low shift out the sign bit of the previous conversion. The next 14 falling edges shift out B13-B0 of the previous conversion. There are a total of 15 data bits because the LTC2311-14 is described as a 14-bit + sign ADC. This could also be considered a 15-bit ADC.

  • thanks for your reply.But i can not understand

    1.why the sign bit (one bit )need two falling SCK edge?  the sign bit is that my care data?

    2. The next 14 falling edges shift out B13-B0 of the previous conversion.it means falling edge shift out data. If my FPGA or mcu want to sample the data  when the SCK rising edge .Maybe  it is not possible to sample data,  because it is possible that the data has not yet shift out.   for example  the 3 falling edge shift out B13  ,but the rising edge  before 3 falling edge cannot sample B13 .  do you have any suggestion?

  • +1
    •  Analog Employees 
    on Dec 14, 2018 3:29 PM in reply to paulkiyt

    1. The ADC requires a total of 16 falling SCK edges to perform conversion. The ADC outputs 15 bits of data (sign + 14bits). There is going to be one bit of extra data which could have been 0, 1, sign bit, LSB. The designer decided sign bit.

    2. From the falling edge of SCK until next bit is valid is a maximum of 7.4ns. To shift data at maximum 5Msps requires a SCK period of 9.5ns. Data will not necessarily be present on rising edge, therefore it is necessary to use falling edge. Data remains valid after falling edge for 2ns which is adequate for most FPGA.