AD9208 Startup & Debug

Hello,

I am using the AD9208-3000EBZ with the Xilinx VCU108 Dev Board. I am having trouble getting the AD9208 to initialize correctly. When probing the JESD IP signals on the FPGA side, it appears to initialize and come out of reset as expected, then nothing else happens. It's almost as if the AD9208 never sends any CGS characters, or anything at all, which leads me to believe I am not initializing it properly. The first image is a screenshot from the AD9208 Datasheet pg72 "Setting up the Digital Interface".

Note: I am attempting to use Subclass0 as an initial test.

As you can see, these instructions leave many questions unanswered. I tried to implement these instructions as best I could (shown in the next screenshot) but the problem was as described earlier.

I then found a question on this forum (https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/99115/ad9208-3000ebz-schematic/296504#296504) which leads me to the datasheet for the AD9689 pg81. I then tried to implement this sequence with the following code, but also to no avail:

This final screenshot is one of my JESD IP signals. As you can see, the QPLL has locked, the IP has exited reset, but SYNCtvalid , and SYSREF are never asserted and tdata remains 0.

  

Any insight? I'm not sure what could be wrong..

*Update*   util_ds_buf_0_IBUF_OUT = SYSREF



signal clarification
[edited by: JacobC at 8:34 PM (GMT 0) on 12 Dec 2018]
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