I am using the AD9208-3000EBZ with the Xilinx VCU108 Dev Board. I am having trouble getting the AD9208 to initialize correctly. When probing the JESD IP signals on the FPGA side, it appears to initialize and come out of reset as expected, then nothing else happens. It's almost as if the AD9208 never sends any CGS characters, or anything at all, which leads me to believe I am not initializing it properly. The first image is a screenshot from the AD9208 Datasheet pg72 "Setting up the Digital Interface".
Note: I am attempting to use Subclass0 as an initial test.
As you can see, these instructions leave many questions unanswered. I tried to implement these instructions as best I could (shown in the next screenshot) but the problem was as described earlier.
I then found a question on this forum (https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/99115/ad9208-3000ebz-schematic/296504#296504) which leads me to the datasheet for the AD9689 pg81. I then tried to implement this sequence with the following code, but also to no avail:
This final screenshot is one of my JESD IP signals. As you can see, the QPLL has locked, the IP has exited reset, but SYNC, tvalid , and SYSREF are never asserted and tdata remains 0.
Any insight? I'm not sure what could be wrong..
*Update* util_ds_buf_0_IBUF_OUT = SYSREF
In your first screenshot, the F value was something the AD9208 could not support. For a list of supported modes, please see table 33 on page 72 of the AD9208 Rev0 datasheet.
In your second screenshot, the L.M.F values of 8.2.1 are supported by the AD9208. In this case, the line rate, when clocked at 3GHz will be 15Gbps/lane. 0x056E should be set to 30h which is default. under these conditions, the PLL should read a lock (0x056F = 80h or 88h).
Are you sure
- the FPGA can capture 15Gbps data?
- the FPGA is getting a REFCLK that can decode the data using the CDRs in its transceivers?
Thank you for your response. I see my mistakes, but I still have several questions:
- on the first configuration, the problem persists even after changing to F=4.
- how do I bring the lane rate down? I would like to operate in subclass0, at either 7.5 or 12.5Gbps.
- for the AD9208, must always M=2, or is M=1 allowed? I have read but am still unclear on whether that refers to physical number of ADCs attached to the my single JESD interface, or if that refers to something else. When the AD9208-3000EBZ and ADS7V are configured through ACE with M=1, it seems to work properly but I still don't understand it.
- I am providing a REFCLK to my FPGA that is determined from a target lane rate of 12.5Gbps which should make the REFCLK=312.5MHz, unless I am also misunderstanding this.
As you can probably tell, I am a little lost in all the details right now. Your help is greatly appreciated.
No worries, your statement is correct. I have no reason to believe the lane is actually "dead" as this particular AD9208 works perfect when using ACE and an ADS7-V2 (without the interposer board) and the loopback works perfect within the FPGA. I have ran loopback test patterns and it works fine. I should clarify that I think my interposer board is the reason for the lane being "dead."
Regardless, I think we are getting off topic. My main concern is that when everything is set to use all 8 lanes, K characters come across the link on all lanes except the "dead" one (lane 4) but I want to circumvent this by using any of the lanes beneath lane 4. I have tried using lanes [3:0], lanes [1:0] and lane , but when I place the ADC into any of these modes, I don't see any K characters on any lanes. I am almost positive that this problem is caused by my ADC setup process. I've added a few notes and screenshots below of my Microblaze code that initializes the ADC.
1) Function call from main to init the AD9208 via SPI:
the function that it calls:
same function, continued where last screenshot ended:
2) Initialize the JESD PHY.
3) Init JESD IP within the FPGA for both TX and RX within the same set of physical transceivers. This project mainly uses RX, but TX is instantiated in case internal loopback mode is necessary.
Are you getting a PLL lock (0x056F = 80h or 88h) when you set the ADC to L.M.F = 1.1.2?
If I am not mistaken, you are using a ADC sample clock of 312.5MHz. Is this correct? If so, with L.M.F = 1.1.2, your line rate should be at 6.25Gbps/lane. Are you making sure that you have the lane rate register 0x056E set to the correct value? 0x056E = 10h. This will ensure that the PLL within the AD9208's JESD204B section is locked.
Yes, all registers have the required values after setup. The ADC sample clock is 312.5MHz and the PLL control register (0x056E) is set to 0x10 to give a laneRate=6.25Gbps.
I am assuming you are getting a PLL lock through 0x056F? is it reading 80h or 88h?
I found a solution. It turns out that it was a lane mapping issue as well as a hardware issue. My interposer board had faulty traces which was easily resolved by just trying a different interposer board. The AD9208-FMC-EBZ had mixed up lanes assignments and polarity as a result of routing decisions from ADI, as well when my FPGA implements my JESD PHY, the channel placement is dependent upon the number of lanes you are using and the desired starting location for XCVR placement that is set within the IP. After de-scrambling all this confusion, I am able to establish the link reliably with any number of lanes (while using my interposer board!). Thank you for your help.