Post Go back to editing

External Sync I/O - HSC ADC EVALCZ

Hello,

I am working with HSC-ADC-EVALCZ and AD9279 board. I was hoping if we can externally trigger pulses through the HSC ADC EVALCZ board and do the data capture based on the pulses. 

As for now I have looked around various discussions where it is recommended to find if the AD daughter board supports external pulses or no which in this case is AD9279. Is AD9279 meant to support external pulse triggering?

Further, I have tried the method discussed under AD9649_29_09_TriggeredCapture_QuickStartGuide_PrA.pdf but instead have used the binary file provided Octal_High_Speed_20151104_1315.bin. Using the method provided in the PDF I have been able to  generate a 2.5V on SMA2. While providing a 2.5Vpp square wave signal on SMA1 does not affect the data capture as it keeps on recording data. If I am not wrong, if there are no external trigger on SMA1 then there would not be any data capture happening which is not the case. At one point in the pdf it also says to write 0x02 to address 0x06. This particular address is not mentioned in the datasheet of AD9279. While in the discussion people have mentioned to write 0x01 to address 0x01 but AD9279 address 0x01 is a read only register. So I guess this is writing to some address register of the FPGA of HSC ADC EVALCZ. Would you happen to know which address and what data must be written in the case of AD9279 if it happens to support external triggering.

Any help provided I would be grateful. 

Best Regards

Sitansu Sekhar

Top Replies

Parents Reply Children
No Data