AD9634 PN9 Test

ferris on Dec 6, 2018

I set several test mode of AD9634, and get samples from FPGA as shown below.

I think the three mode(one/zero word toggle, alternating checkerboard, ramp output) are passed. But for PN9 test, there are two zero word. I'm confused. Can someone tell me the correct PN(PN9 and PN23) sequence generation way in AD9364. Thanks very much!

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ferris Dec 7, 2018 +1

Hi J.Harris,

Thanks. I find the problem now. When I slow down the sampling frequency, I have got the exact PN9 sequence. There is no inverted output bit, and the PN sequence is directly mapped to the output…

0 J.Harris

on Dec 6, 2018 2:11 PM
Hi ferris,

The AD9634 PN sequences are nuanced similar to the AD9643/AD9613. Please refer to the following thread for more information on handling the PN sequence for the AD9634: PN Sequence Info.

Regards,

Jonathan
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0 ferris on Dec 7, 2018 2:43 AM

Hi J.Harris,

Thanks. I find the problem now. When I slow down the sampling frequency, I have got the exact PN9 sequence. There is no inverted output bit, and the PN sequence is directly mapped to the output(12 bits), no jump.
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0 J.Harris

on Dec 7, 2018 12:36 PM in reply to ferris
I'm glad you were able to get things working. I thought that this part had a similar nuance in the PN sequences as its dual counterpart, but perhaps those nuances were cleaned up when the single was released since it was after the dual.

It sounds like you may have a timing issue in your FPGA capture preventing you from running at a higher clock rate. You can try adjusting the output DCO delay using register 0x17 to see if that helps you get it working at higher clock rates (alternatively you can adjust timing in the FPGA.
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