AD9271 digital output

Hi Hance,

Thanks for using AD9271. Are you saying that the signal at the DOUT pins are not toggling (not even noise), or are they toggling but you do not see your test signal?

Thank you.

Doug

Hi Doug,

I tried many methods but failed to solve the problem.The voltage of the power pin is correct.The acquisition frequency is also correct.Can I get some advice from you?

Thank you.

Hance

Hi Hance,

Can you try the digital test patterns, which are enabled by writing to Register 0x0D? The list of possible patterns is in the AD9271 datasheet RevB Table 15 on page 39. You can place known patterns on the outputs to see if you are capturing correctly.

Please give this a try.

Thank you.

Doug

Hi Doug,

I tried the digital test patterns,but it's still the same thing.I don't know if there is something wrong with my test program. I paste it on the page.Can you give me some advice?

Thanks a million.

Hance

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SPICTL1 is

         Port (      

                                   fosc                                            :               in std_logic;                                                                   --system clock

                                   glrn                                   :               in std_logic;                                                                  --globe reset                                     

                                   csb                                :            out std_logic;                                                               --cs low

                                   sclk                                     :          out std_logic;                                                               --min25MHz

                                   sdi                                 :                 in std_logic;                       --sck low-up

                                   sdo                                :                 out std_logic                       --sck up-low

                          );

end SPICTL1;

architecture Behavioral of SPICTL1 is

                  signal f_csb                             : std_logic :='0';

                  signal f_sclk                            : std_logic;

                  signal buffer1          :std_logic_vector(15 downto 0);

                  signal buffer2          :std_logic_vector(7 downto 0);

                  type st is (st0,st1,st2,st3,st4,st5);

                  signal st_state                  : st;

begin

                  csb <= f_csb;

                  sclk <= f_sclk;

                  process(glrn,fosc)

                  variable cnt1                    : integer range 0 to 15 :=15;

                  variable cnt2                    : integer range 0 to 7 :=7;

                  begin

                          if glrn = '0' then

                                   f_csb <= '1';

                             buffer1<= "0000000000001101";       --0x00D

                             buffer2<= "00001001";                                        --1001                                                                          

                                   cnt1 :=15;

                                   cnt2 :=7;

                          elsif fosc'event and fosc='1' then

                                   case st_state is

                                            when st0 =>

                                                     f_csb <= '0';

                                                     st_state <= st1;

                                            when st1 =>

                                                     f_sclk <= '1';

                                                     sdo <= buffer1(cnt1);

                                                     st_state <= st2;

                                            when st2 =>

                                                     f_sclk <= '0';

                                                     if cnt1 = 0 then

                                                             st_state <= st3;

                                                     else

                                                             cnt1 := cnt1-1;

                                                             st_state <= st1;

                                                     end if;

                                            when st3 =>

                                                     f_sclk <= '1';

                                                     sdo <= buffer2(cnt2);

                                                     st_state <= st4;

                                            when st4 =>

                                                     f_sclk <= '0';

                                                     if cnt2 = 0 then

                                                             st_state <= st5;

                                                     else

                                                             cnt2 := cnt2-1;

                                                             st_state <= st3;

                                                     end if;

                                            when st5 =>

                                                     f_csb <= '1';

                                                     st_state <= st5;

                                            when others =>

                                                     st_state <= st0;

                                   end case;

                          end if;

                  end process;

end Behavioral;

Hi Doug.

I am not quite sure whether there is any defect in my receiving circuit, so I submit my circuit diagram, hoping to get your advice.

Thank you.

Hance

Hi Hance,

I'm sorry but I'm not a good one to ask about reviewing your test program. Would it help you if I could find some sample FPGA source code that shows how we capture the outputs on our FPGA board?

Regarding your schematic, would you please provide a more complete version? The attachment shows only a small portion of the circuit and it is difficult for me to see what signals are connected to the AD9271.

Thank you.

Doug

Hi Doug,

I would appreciate it if you could provide some sample FPGA source code that shows how we capture the outputs on our FPGA board.

The picture is too big for me to take all screenshots.The following picture includes the signal transmission and acquisition part of my circuit, as well as the configuration part of AD chip.The receiver of the eight channels is the same circuit, so I don't have all the screenshots.

I really appreciate your help.

Hance

Hi Hance,

I'll need to ask my colleague about a more detailed look at your schematic. It is still hard for me to read. I see busses going off-page and I cannot tell how they are connected back to the part.

Here are some example of FPGA capture code for similar parts.

This is sample code for ADCs with octal serial LVDS outputs similar to AD9271. This is written for Xilinx Virtex4

This is sample code for a 16 channel ADC that also has serial LVDS outputs similar to AD9271. This is written for Xilinx Virtex6.

These examples are provided freely, as-is, and without guarantee.

Thanks,

Doug

Hi Doug,

Thank you very much for the FPGA capture code you provided.I will study it carefully and try rewriting the control program again.I have submitted the circuit diagram. Can you help me check what's wrong there?

Christmas is approaching, early to wish you Merry Christmas! Best Regard!

Thanka,

Hance

sod1.4.PDF

Hi Hance,

Belated Merry Christmas!

Have you verified that your SPI interface to AD9271 is working? Can you read register values and see if the contents are as expected? For example, what do you see when you read Register 0x00 and Register 0x01?

Also, have you confirmed that the desired values you write are really getting written to the SPI registers? Please remember you need to issue a transfer bit (Register 0xFF Bit0) after your desired SPI sequence, for them to take effect. Please see the "READING THE MEMORY MAP TABLE" section of the AD9271 datasheet for more information.

I'm not the main support for AD9271. I've asked one of my colleagues to look at your circuit but he is still out on holiday. I hope he can look into it after he returns.

Thanks,

Doug

Hi Dougl! this link you share die, can you send me it?

my email: viettranbme@gmail.com

Hi Viet,

Thank you for your question. Would you please confirm what information you are looking for?

Thank you.

Doug

Hi Viet,

Thank you for your question. Would you please confirm what information you are looking for?

Thank you.

Doug