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Syncing multiple AD6655


Can someone share a scheme which shows how to sync multiple AD6655 units?

I try to sync 4 channels of 2 AD6655 using a synced clock of 100MHz, sync signal, and configuring register 0x0ff with 1 simultaneously, Reading the user-guide from cover to cover several times. I believe that these are the three requirements for the signals to be synced.

The 2 AD6655 transmit the data using FPGA into a DSP memory. 

When I use a checkerboard  test signal (see AN-877), the signals from the 4 channels in the DSP memory are identical. (PS. The user guide of the AD6655 is inaccurate, test signal 4 seems to be supported by the AD6655, though it is changed by the NCO and/or the FIR filter.).

When injecting a common signal to the 4 channels, and computing the Bode plot between channels from different AD6655, I see a linear phase, which indicate a time shift between the outputs of the twe ICs. The group delay is constant unless I reset the system. No group delay is identified between channels from the same AD6655.

Can anybody help me with this strange behaviour of this almost excellent ADC?

Thank you in advance for your help. 


  • Hello,

    I am not sure if I understand the issue correctly. Below comment is based on assuming that the issue is the synchronizing multiple AD6655 as like title. There is a constant time shift(phase delay) on the outputs of the two ICs, but not on the channels for the same IC.  

    Phase relationship is not deterministic and can vary for multiple channels/devices on the same board and varies from startup to startup. .  To address this, a SYNC input on AD6655 is offered that allows for the resetting the phase of the internal blocks(The input clock divider, NCO, half-band filters, and signal monitor block) at a known instance. 

    When the clock divider is used, there will be multiple edges of the applied clock for every sampling edge. Using the SYNC pin will reset the clock dividers of multiple AD6655s so they are all in the same state, and thus the same edge of the applied(pre-divided) clock(CLK+/-) is the sampling edge on all devices. In other words, the clock will be divided down at the edge where SYNC signal comes and they will be synchronized. And internal blocks within a single part or across multiple parts can be synchronized at the synchronized timing with SYNC signal.  

     The SYNC function does not adjust the sample clock edges(phase) itself for devices and instead it allows ADCs sampled at the same edge. So if you are using multiple sources, make sure to align clock and sync signals for multiple channels/devices externally. One suggestion is HMC7044 that would be a good choice for clock and sync(refer to the figure 127 on AD6676 datasheet as reference). Its ability to individually control the delays of both the clock and sync signals to each ADC device allows compensation of PCB skew delays.  And make sure the logic level and timing requirements specified in datasheet for Sync. I wish this helps.



  • Hello Tony,

    I appreciate your exhaustive answer which starts with an accurate description of our problem. All this is known, and was checked, as we have RTFMed this issue thoroughly. Still, we encounter a linear phase between two channels from different ICs.  

    Also, we are using LMK04828 to clock and sync the ICs, which is much like you suggested HMC7044.

    So far, we didn't discover any problem with the clock and the sync signals, all seem to be aligned to the same phase at the input to the ICs.

    We obviously miss something, and would like to have a close support on this issue, as we spent too much time to troubleshoot this strange behavior. Is it possible to have a prompt dialog with you, including sending schemes and a list of tests done?

    Thanks, Alon. 

  • Hello Alon,

    It is sorry to hear there is still issue. Please email me ( for further communication.

    I am sure you checked below already. But just  in case, I copy the logic level and timing requirement of sync signal.


    And how did you set reg.0x100 (register for Sync Control), reg.0x101 bit [1:0] (fs/8 sync) ? and reg.0x122 & reg.0x123 (register for NCO Phase Offset) on ADC ICs?

    When you say " a linear phase difference " between different ADC ICs,

    1. is there fixed phase difference in +/-1 clock range? or if  there is a fixed clock delay, how many clock delay there is?

    2. does it vary from startup to start up?

    3. Is there any change at two cases below :

          case 1 : reg.0x100 with 0x00 & reg.0x101 [1:0] with 0b 00

          case 2:  reg.0x100 with 0xff   & reg.0x101 [1:0] with 0b 11

    4. Is there any change by adjusting reg.0x122 and reg.0x123 (NCO Phase offset, refer to Phase offset on page 38 ) where reg.0x100 bit [4:3] were set at either 0b01 or 0b11?