Can someone share a scheme which shows how to sync multiple AD6655 units?
I try to sync 4 channels of 2 AD6655 using a synced clock of 100MHz, sync signal, and configuring register 0x0ff with 1 simultaneously, Reading the user-guide from cover to cover several times. I believe that these are the three requirements for the signals to be synced.
The 2 AD6655 transmit the data using FPGA into a DSP memory.
When I use a checkerboard test signal (see AN-877), the signals from the 4 channels in the DSP memory are identical. (PS. The user guide of the AD6655 is inaccurate, test signal 4 seems to be supported by the AD6655, though it is changed by the NCO and/or the FIR filter.).
When injecting a common signal to the 4 channels, and computing the Bode plot between channels from different AD6655, I see a linear phase, which indicate a time shift between the outputs of the twe ICs. The group delay is constant unless I reset the system. No group delay is identified between channels from the same AD6655.
Can anybody help me with this strange behaviour of this almost excellent ADC?
Thank you in advance for your help.