I'm working on an FPGA code to interface AD9613 to xilinx Zynq (artix 7). I'm hoping to get some help on how to align data clock edge to the center of data eye. There is a xilinx 7 series IP called IDELAYE2 that design to correct the phase alignment, but I can't find any documentation online that explain how to determine the delay tap. Really appreciate if you can guide me on how to do the phase alignment, especially how to determine the delay tap count.
Kheng Oon Lim