AD9680 Design


    I'm planning to use AD9680 to develop a reciever system. There's some issues confusing me, can anybody answer my questions?

1. I found that there are two evaluation boards for AD9680, one named 9680CE04B and another named 9680CE02B. They are used in different frequency band. What the purpose for you to make these two boards? And what the detail difference between these two boards?

2. To achive the SNR specification in all avaliable frequency band of AD9680, there should be a clock source with very low jitter, maybe less than 100fs in all encode band.  It's maybe very difficult. 

May I use an ultra low phase noise clock oscillator to provide sample clock for AD9680, at the same time use a clock source to generate SYSREF for AD9680 and SYSREF and serdes clock for FPGA? Can it be work?  

Waiting for reply. Thank you!

Top Replies

    •  Analog Employees 
    Nov 5, 2018 in reply to ray·huangfu +1 verified
    If I use a crystal oscillator to clock AD9680 and use HMC7044 to provide other clocks for system(sysref for AD9680 and FPGA in subclass 1 application,serdes clock for FPGA), can the sampling…