We currently have a working design that uses an input clock of 491.52 MHz in full bandwidth mode.This design uses one JESD lane @ 9.83GHz. This provides JESD receive interface that presents 2 samples per 245.76 MHz clock period.
I wish to change the design to allow an input clock of 983.04 MHz (doubling the clock rate). But I want the ADC to decimate x2 so that the the data rate is still the same (1 JESD lane, 2 samples per 245.76 clock) remains the same. Is this possible ? It looks like I should be able to do it with one DDC (per ADC channel). And using the Fs/4 NCO programming with HB1+HB2.
Do I need to program coefficients for the filters ? Is there an example configuration that is similar to this? Thanks, -Bruce