i am a little bit in trouble with the HMCAD1511 evaluation board. I am using this board connected to my Zedboard and i want to generate the 1GHz sampling clock on board.
Since the Zedboard i have is not capable of creating such signal, i want to solder the PLL chip on the HMCAD1511 board. I searched on the Hardware User Guide of the board
(here is the link to the document: https://www.analog.com/media/en/technical-documentation/evaluation-documentation/hardware-users-guide-140-00036-00-15xx.pdf)
and in the part list is only referred as "do not mount" component.
Does anyone have the complete part list for the board? it will really save me time.
Thanks for the help.
i had time to search for the piece i was missing. The clock generator used on the HMCAD1511 board is the Texas instruments CDCE421A.
Link to the page is : http://www.ti.com/product/CDCE421A/support
Hope someone can take advantage of this information, thanks anyway ;)
Thank you very much for your post, your answer is quiet helpful, I'm looking for the on board 1GHz clock solution as well, the crystal PCB footprint for the CDCE421A on the Eval01-HMCAD1511 board is quiet unusual, I think I should find a 31.25MHz passive crystal, but still unable to find a suitable component that could fit in the board. Are you able to find the correct component type and vendor? Thanks!
Hello Kratos, i am confused if the bandwidth of HMCAD1511 is up to 300MHz when use one channel mode, could you help me?
Hi ! pangzegui
I had the same problem. I wasnt' able to find the correct 31.25 MHz crystal to fit the footprint on the PCB.
Thankfully i had this board connected to an FPGA from which i generated a 31.25 MHz signal and routed it to the HMCAD1511 board feeding the Ti chip.
Hi Ihjhit !
I am a little bit confused by the question but i'll try to answer.
When you want to sample at 1 Gbps with this chip, you have to feed it with an external 1 GHz clock. That said, if you are using the single channel mode at 1G the chip uses all 4 internal ADC interleaved (so each of them is sampling at 250 MHz with a known phase shift wrt to the others). So in the fastest mode that the chip can handle the max sample frequency that the single ADC handle is 250M but the whole throughput will be 250M x 4.
Hope this solve your doubt.