We use LTC2312-12 and supply CONV and SCK by FPGA.
Our environment setup:
VDD : 3.3V
V_REF: 2.054V (measured)
OVDD : 3.3V (from our FPGA)
According to Page 14 Figure 11 in datasheet, our A_IN and output code follow the tendency when A_IN is under 1 V,
but when the A_IN exceed 1V , we found that our MSB of SDO didn't turn to 1 as A_IN increase and other 11 bits still follow the tendency.
Our setup follows the Page 1 Figure and the other specification.
Is their anything we need to concern about?
Do you have any ideas about the cause of this issue?