LTC2312-12 SDO MSB No toggle

Hi Ted,

Can you provide a schematic of your ADC input driver and an oscilloscope photo showing CONV, SCK and SDO? Also please provide a photo of your setup.

Hi ghoover,

Thanks for reply.

Our setup follow page 1 of the datasheet  but add a RC filter (like Figure 10 in datasheet) on A_IN, the schematic is followed as figure (a).

                                                  (a)

The setup of our experiment are photoed as follow, the resistance and the capacitor is  weld behind the circuit board :

                              (b)                                                                                                   (c)

In picture (b),

Left side

Red     -- VDD : 3.3V with a 2.2uF capacitor connect to GND
Purple -- REF : measured 2.054V, also a 2.2uF capacitor connect to GND
Black   -- GND :
Blue     -- A_IN : connect to a RC(50 ohm, 47pF), the voltage come from VDD and the value is managed by using two variable resistance (both 10 kohm)

Right side

Green -- CONV : input from FPGA, t_conv is about 356ns in our experiment (can be adjusted)
Orange -- SCK : input from FPGA, approximately 8 MHz in our experiment (can be adjusted)
Blue      -- SDO : output to FPGA
Red     -- OVDD : 3.3V  come from FPGA

All of our GND is connect to one place (show in picture (c)), including power supply, oscilloscope, FPGA, GND with each capacitor, etc.

We have also added a resistance(33 ohm) on SDO, but it didn't approve the MSB issue either.

The oscilloscope photo showing CONV, SCK and SDO are listed as follow:

   
                                                 (d)                                                                                                                     (e)

In picture (d) and (e),

A_IN is supplied by 0.989V and 2.019V, respectively.
Both condition should let the MSB of SDO be 1, but our experiment show that the MSB is always 0 while other 11 bits has the tendency of increment.

We also show the t_conv(356 ns) and t_2(56 ns) in picture (f) and (g)

   
                                               (f)                                                                                                           (g)

Thanks for help!

Hi Ted,

To get good performance when using this ADC you really should have a PCB with a ground plane.

Using long unshielded wires for the digital signals between the FPGA board and the ADC board will result in ringing as you see in your oscilloscope traces. If this ringing is more than a diode drop above VDD or below GND you risk damaging the ADC at worst and at a minimum this will compromise the ADC performance. You should also have a low inductance ground connection between the FPGA board and ADC board.

The data sheet clearly states that the output impedance of the signal driving the analog input should be less than 50ohms. The 10kohm resistor divider you are using to drive the ADC is clearly well above this limit. I suggest buffering the resistor divider with an op amp buffer. The LT6230 or LT1818 are two op amps to consider.

Looking at your timing, the CONV signal should stay high for a minimum of 1.4uS before going low and starting to clock out the data. This will allow the ADC time to complete the conversion.

You might consider looking at the DC1563A-C which is the demo board for the LTC2312-12 for layout guidance when you make your own PCB or you may even want to purchase a DC1563A-C to evaluate the LTC2312-12 performance.

Let me know if you have any more questions.

Hi Ted,

To get good performance when using this ADC you really should have a PCB with a ground plane.

Using long unshielded wires for the digital signals between the FPGA board and the ADC board will result in ringing as you see in your oscilloscope traces. If this ringing is more than a diode drop above VDD or below GND you risk damaging the ADC at worst and at a minimum this will compromise the ADC performance. You should also have a low inductance ground connection between the FPGA board and ADC board.

The data sheet clearly states that the output impedance of the signal driving the analog input should be less than 50ohms. The 10kohm resistor divider you are using to drive the ADC is clearly well above this limit. I suggest buffering the resistor divider with an op amp buffer. The LT6230 or LT1818 are two op amps to consider.

Looking at your timing, the CONV signal should stay high for a minimum of 1.4uS before going low and starting to clock out the data. This will allow the ADC time to complete the conversion.

You might consider looking at the DC1563A-C which is the demo board for the LTC2312-12 for layout guidance when you make your own PCB or you may even want to purchase a DC1563A-C to evaluate the LTC2312-12 performance.

Let me know if you have any more questions.

Hi ghoover,

Thanks for reply again.

We will try to approve our experiment environment.

But for the time of staying high of the CONV signal, we follow the datasheet of  "2.5Msps Throughput Rate", which is different from the "500ksps Throughput Rate".

The former one said the minimum of t_conv is 247 ns while the latter one is 1.4 us.

How can we distinguish our part is 2.5M or 500k throughput Rate?

The LTC2312-12 maximum conversion rate is 500ksps. You would need to use the LTC2313-12 if you wanted to run at 2.5Msps.

Sorry for my mistake of the wrong title.

The part we use is LTC2313-12.

Your CONV timing is OK for LTC2313-12. The demo board for you to look at is the DC1563A-B. All other comments about PCB with GND plane, shielded wires, and output impedance still apply.

We have tried to modify our setup according to your suggestion as possible as we can.

Now we have the SDO MSB as we expect. For example, the figure below show the A_IN = 2V when VDD = 3.3V. 

The value of SDO is increase when supply of the A_IN increase. But it is not that stable when  the voltage of A_IN does not change.

Is the SDO of the same value of A_IN will be totally the  same at next conversion? Or there is an interval for toleration?

Still we collect the data increment tendency and  make a diagram like the Figure 11 in datasheet as follow.

It didn't make sense that the curve is not progressively increase. Are we still have anything to deal with?

Also we have observed that when we don't give any CONV and SCK but only supply the VDD, we can measure the V_REF at 2.058 V, but after several phase of CONV and SCK being supplied, although we can get the SDO value, the V_REF will change to 2.289V. This condition confused us, too.

Last but not the least, we also consider to use the DC1563A board.

Our ideal thought is to connect our FPGA (which supply CONV, SCK, and receive SDO) directly to the demo board. Is the region I circle out  in the figure is for this kind of use? Otherwise, is that the only way is to use the Altera chip to modify the CONV, SCK and SDO ? It seems that the manual is not clearly for our use.

All of our purpose is to get the stable and correct SDO for our latter SoC design.

Sorry for asking so much question at a time!

You do not state specifically which suggestions you have implemented. Do you have a PCB with a ground plane? Have you shielded the wires between the FPGA board and ADC board? Have you shorted the board grounds with a low inductance connection? Have you buffered the ADC input voltage with an op amp? If so please provide a schematic of the buffer circuit. If not see Figure 10 of the LTC2313-12 data sheet for an example buffer circuit.

For best performance the bypass capacitors for VDD, VCCIO and Vref should be connected as close to the ADC pins as possible and as close to the ground plane as possible. This will reduce noise. The REF pin bypassing is particularly critical. REF is not a static node. During each conversion a series of bit tests are performed that cause glitches at the REF pin. If not properly bypassed the REF pin will not be kept steady and the conversion will not be accurate.

You can connect CONV(CSL), SCK and SDO directly from your FPGA board to the DC1563A. It is necessary to use shielded wires between the two boards and to tie pin 2 of J3 to 3.3V so that the MAXII CPLD on the DC1563A knows that an external controller is being used so that the MAXII does not send signals to the ADC. 

Sorry for that we do not follow the suggestion you give to us.

The ADC is only the part of our design, the output of the ADC(SDO) will be the input of  a PWM circuit design. So our PCB may contain other element in the feature.

To state specifically,

1.Do we have a PCB with a ground plane? --> Hard to get our own PCB with a ground plane now.

2.Have we shielded the wires between the FPGA board and ADC board? --> working on it, what we have now is the unshielded wire you have seen in the photo before. On the other hand, our pin on FPGA used GPIO pin to connect out, is that possible to connect shielded wire too?

3.Have we shorted the board grounds with a low inductance connection? --> sorry that we don't sure about how to reduce the inductance between FPGA and ADC board.

4.Have we  buffered the ADC input voltage with an op amp? --> No, we don't have this kind of element now.

Our purpose is try to experiment our algorithm since the ADC is one part of our flow design. And we try to setup and want to get a stable SDO from the ADC first. But it  look like our environment is totally not  qualified.

As the all point that we have mentioned above, we may take the DC1563A-B as consideration.

By using our FPGA to send CONV, SCK and receive SDO, we still not sure about how to connect all 8 pins of the ADC. 

VDD --> ?
REF --> ?
GND --> in the board
AIN --> J4 (Is there already an op amp like LT1818 in the board? We can't see in the schematic diagram of DC1563A)
CONV --> directly from our FPGA
SCK --> directly from our FPGA
SDO--> directly to our  FPGA
OVDD --> tie pin 2 of J3 to 3.3V?

Is there any other pin or setup we need to concern when using DC1563A-B ?

Also, we notice that there is an Altera chip on the board, is it a FPGA chip for us to modify or we should not do anything about it?

Again, thanks for your reply with patient every time.

Apply 9V and GND to the indicated terminals on the DC1563A-B. This will provide all necessary DC bias (VDD, OVDD and REF) to the board. OVDD is jumper selectable between 2.5V and 3.3V. Select the correct voltage for your FPGA.

Use shielded wires to connect CONV, SCK and SDO from the FPGA board to the DC1563A.

Tie pin 2 of J3 to 3.3V.

There is not a driver circuit on DC1563A. DC417B is an unstuffed board onto which the LT1818 driver circuit can be placed. Connect DC417B to DC1563A-B using the BNC connectors(J4 on DC1563, J5 or J2 on DC417B depending on which package selected).

The Altera MAXII is a CPLD that by default is used to deserialize the ADC data, when  connected to a DC718 controller. You could reprogram the MAXII with your own code if it will fit within the memory of the MAXII and then not require a separate FPGA board. Otherwise just tie pin 2 of J3 to 3.3V and the MAXII will not try to communicate with the ADC.

Is DC417B necessary  when we use DC1563A for our design?

DC417B is not necessary. It is an easy way to add a driver to the DC1563A. A driver is necessary unless your signal source has a low (less than 50ohms) output impedance.