I am using the AD9694 and I have problem with the A/D convertion that does not start.
The input clok is 500 MHz and the analog input signal is 10MHz 800mVpp (AC coupled).
If I set the A/D in test mode forcing a ramp generation (writing the register 0x0550 0x0f) all is working correctly.
Which could be the cause that put the A/D not converting (all 4 channels) ?
Following my startup initialization:
0x12 0x28 0x4F0x12 0x28 0x0F0x12 0x22 0x040x12 0x22 0x000x12 0x62 0x080x12 0x62 0x00
0x00 0x02 0x11
# quick configuration (Lines = 2, Converters (M) = 2, Octets x frame (F) = 2) b"01-001-001"0x05 0x70 0x49
# N', N, CS0x05 0x8F 0x0F0x05 0x90 0x2F
0x05 0x8B 0x00
0x01 0x1c 0x0A
#set line rate 5GBps
0x05 0x6E 0x10
# Normal Mode0x00 0x02 0x00
Someone can help me how and what I have to investigate ?
What are you seeing at the output of the AD9694 when the "the conversion does not start"?
many thanks for your help.
Below it is reported an acquisition on RX side when the conversion does not start, in particular on my bench I have channel A input a sine wave (14 MHz, 800 mVpp), channel B open, channel C open, channel D open.
rx_rxdata are inconsistents and rxcharisk always recognize a K char (rx_sync always set to 1).
If I set the A/D in test mode to generate a ramp (0x0550 0x0f) I obtain the following result (all seem working properly):
rx_rxdata are consistents (ramp) and rxcharisk always set to 0.
Considering the first figure it seems that the analog input is not acquired, both when the signal is applied or left open.
Which could be the cause ? What should be investigated ?
I have set the register 0x0571 = 0x16 and then also 0x0571 = 0x02
In both cases all seems working correctly (but this configuration is for debug only).
What does it means ? Where I have the problem and what I have to investigate?
This looks to me that the FPGA program is not interpreting character replacement correctly.
Setting 0x571 to 1 would turn off character insertion, and that explains why there is no longer k characters in the JESD link.
Please keep in mind that K characters in the JESD link doesn't necessarily mean the link is broken. The FPGA program should be able to handle character replacement.
rgetz is there any suggestion you can offer to help Maurizio? Is there a FACI character replacement enable on the FPGA side?
If the ADI-JESD204-IP is used, FACI character replacement is available only when scrambling is enabled
The FPGA use the Xilinx IP: JESD204_PHY (v3.4) and JESD204 (v7.1) to directly interface and decode the JESD protocol.
The problem is present both with scrambling enabled or disabled and when the input analog signal is greater than 100mVpp .
If I set the register 0x571 = 0x16 all is working correctly indipendendently of the level of the input signal.
Which is your opinion ?
I've looked over their documentation for the IP and they don't seem to have any issue related to FACI character replacement. Maybe you can post the question on the Xilinx forums, as they have a more intimate knowledge of the IP. It's possible that there's a misconfiguration in software also for their IP.