AD9694 do not start convertion

Good morning

I am using the AD9694 and I have problem with the A/D convertion that does not start.

The input clok is 500 MHz and the analog input signal is 10MHz 800mVpp (AC coupled).

If I set the A/D in test mode forcing a ramp generation (writing the register 0x0550 0x0f) all is working correctly.

Which could be the cause that put the A/D not converting (all 4 channels) ?

Following my startup initialization: 

0x12 0x28 0x4F
0x12 0x28 0x0F
0x12 0x22 0x04
0x12 0x22 0x00
0x12 0x62 0x08
0x12 0x62 0x00

0x00 0x02 0x11

# quick configuration (Lines = 2, Converters (M) = 2, Octets x frame (F) = 2) b"01-001-001"
0x05 0x70 0x49

# N', N, CS
0x05 0x8F 0x0F
0x05 0x90 0x2F

#disable scrambling

0x05 0x8B 0x00

#enable DCS

0x01 0x1c 0x0A

#set line rate 5GBps

0x05 0x6E 0x10

# Normal Mode
0x00 0x02 0x00

Someone can help me how and what I have to investigate ?

Best Regards

MaurizioB

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Parents Reply
  • Hi Adrian

    The FPGA use the Xilinx IP: JESD204_PHY (v3.4) and JESD204 (v7.1)  to directly interface and decode the JESD protocol.

    The problem is present both with scrambling enabled or disabled and when the input analog signal is greater than 100mVpp .

    If I set the register 0x571 = 0x16 all is working correctly indipendendently of the level of the input signal.

    Which is your opinion ?

    Best Regards

    mauriziob

Children
  • 0
    •  Analog Employees 
    on Dec 7, 2018 3:06 PM over 1 year ago in reply to mauriziob

    I've looked over their documentation for the IP and they don't seem to have any issue related to FACI character replacement. Maybe you can post the question on the Xilinx forums, as they have a more intimate knowledge of the IP. It's possible that there's a misconfiguration in software also for their IP.

    Regards,

    Adrian