AD9694 do not start convertion

Good morning

I am using the AD9694 and I have problem with the A/D convertion that does not start.

The input clok is 500 MHz and the analog input signal is 10MHz 800mVpp (AC coupled).

If I set the A/D in test mode forcing a ramp generation (writing the register 0x0550 0x0f) all is working correctly.

Which could be the cause that put the A/D not converting (all 4 channels) ?

Following my startup initialization: 

0x12 0x28 0x4F
0x12 0x28 0x0F
0x12 0x22 0x04
0x12 0x22 0x00
0x12 0x62 0x08
0x12 0x62 0x00

0x00 0x02 0x11

# quick configuration (Lines = 2, Converters (M) = 2, Octets x frame (F) = 2) b"01-001-001"
0x05 0x70 0x49

# N', N, CS
0x05 0x8F 0x0F
0x05 0x90 0x2F

#disable scrambling

0x05 0x8B 0x00

#enable DCS

0x01 0x1c 0x0A

#set line rate 5GBps

0x05 0x6E 0x10

# Normal Mode
0x00 0x02 0x00

Someone can help me how and what I have to investigate ?

Best Regards

MaurizioB

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  • +1
    •  Analog Employees 
    on Oct 16, 2018 1:08 PM over 2 years ago

    Hi,

    What are you seeing at the output of the AD9694 when the "the conversion does not start"?

    Judy

  • Hi Judy,

    many thanks for your help.

    Below it is reported an acquisition on RX side when the conversion does not start, in particular on my bench I have channel A input a sine wave (14 MHz, 800 mVpp), channel B open, channel C open, channel D open.

     rx_rxdata are inconsistents and rxcharisk always recognize   a K char  (rx_sync always set to 1).

    If I set the A/D in test mode to generate a ramp (0x0550 0x0f) I obtain the following result (all seem working properly):

    rx_rxdata are consistents (ramp) and rxcharisk always set to 0.

    Considering the first figure it seems that the analog input is not acquired, both when the signal is applied or left open.

    Which could be the cause ? What should be investigated ?

    Best Regards

    MaurizioB

  • 0
    •  Analog Employees 
    on Nov 9, 2018 8:12 PM over 2 years ago in reply to mauriziob

    Hi Maurizio,

    How do you determine that the data is incorrect?

    Character replacements take place for frame alignment, so it is not unusual to see K characters in the JESD link. Could you please try turning off character replacement using register 0x0571 (0x0571[1] = 1)?

    Judy

  • Hi Judy,

    I have set the register 0x0571 = 0x16 and then also 0x0571 = 0x02

    In both cases all seems working correctly (but this configuration is for debug only).

    What does it means ? Where I have the problem  and what I have to investigate?

    Many thanks

    mauriziob

  • 0
    •  Analog Employees 
    on Dec 6, 2018 10:38 AM over 1 year ago in reply to mauriziob

    Hi,

    This looks to me that the FPGA program is not interpreting character replacement correctly.

    Setting 0x571[1] to 1 would turn off character insertion, and that explains why there is no longer k characters in the JESD link.

    Please keep in mind that K characters in the JESD link doesn't necessarily mean the link is broken. The FPGA program should be able to handle character replacement.

    is there any suggestion you can offer to help Maurizio? Is there a FACI character replacement enable on the FPGA side?

    Judy

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  • 0
    •  Analog Employees 
    on Dec 6, 2018 10:38 AM over 1 year ago in reply to mauriziob

    Hi,

    This looks to me that the FPGA program is not interpreting character replacement correctly.

    Setting 0x571[1] to 1 would turn off character insertion, and that explains why there is no longer k characters in the JESD link.

    Please keep in mind that K characters in the JESD link doesn't necessarily mean the link is broken. The FPGA program should be able to handle character replacement.

    is there any suggestion you can offer to help Maurizio? Is there a FACI character replacement enable on the FPGA side?

    Judy

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