I am trying to set up a JESD204B serial data link between the AD9683 (AD9683-250EBZ with FMC) and a Xilinx zc706 development board. I have created an SPI interface and am trying to use the AD9683's test pattern to debug the link. JESD204 IP blocks have been used in Vivado for the Rx.
ILAs are being used to monitor the output of both the PHY and RX blocks in the Vivado project. The 32 bit rxdata output from the PHY block is outputting /K28.5/ character (0xBC) before the test mode is enabled, indicating the CGS phase. The user test pattern is set up with 55ffaa33. Enabling the continuous user test mode (writing 0x15 to address 0x61) causes the rxdata output to change to something loosely resembling the test pattern (78b5ff4a) without apparently going through the ILAS phase? All output signals from the JESD Rx block are 0 including sync which needs to be deasserted before the ILAS phase is entered. Is the Rx block not receiving the /K28.5/ character correctly which is preventing the Sync signal from going high? Subclass 0 should be sufficient for the task but enabling it in the memory map registers has no effect.
The system clock for the FPGA (200MHz) is being output to SMAs on the dev board which is then being used to reference the ADC (CLK+-). Is the quality of this clock insufficient to reference the ADC? Vivado clock wizard is being used to divide the system clock where needed.
Any tips on ADC setup, Vivado JESD IP blocks or clocking would be greatly appreciated. Thanks. Calum