AD9683-250EBZ JESD204B Link Synchronisation

Hello,

I am trying to set up a JESD204B serial data link between the AD9683 (AD9683-250EBZ with FMC) and a Xilinx zc706 development board. I have created an SPI interface and am trying to use the AD9683's test pattern to debug the link. JESD204 IP blocks have been used in Vivado for the Rx.

ILAs are being used to monitor the output of both the PHY and RX blocks in the Vivado project. The 32 bit rxdata output from the PHY block is outputting /K28.5/ character (0xBC) before the test mode is enabled, indicating the CGS phase. The user test pattern is set up with 55ffaa33. Enabling the continuous user test mode (writing 0x15 to address 0x61) causes the rxdata output to change to something loosely resembling the test pattern (78b5ff4a) without apparently going through the ILAS phase? All output signals from the JESD Rx block are 0 including sync which needs to be deasserted before the ILAS phase is entered. Is the Rx block not receiving the /K28.5/ character correctly which is preventing the Sync signal from going high? Subclass 0 should be sufficient for the task but enabling it in the memory map registers has no effect.

The system clock for the FPGA (200MHz) is being output to SMAs on the dev board which is then being used to reference the ADC (CLK+-). Is the quality of this clock insufficient to reference the ADC? Vivado clock wizard is being used to divide the system clock where needed.

Any tips on ADC setup, Vivado JESD IP blocks or clocking would be greatly appreciated. Thanks. Calumrx_data JESD PHY block 0xBCAD9683 JESD Vivado Design

  • 0
    •  Analog Employees 
    on Oct 18, 2018 7:44 PM over 2 years ago

    Hello,

    A JESD 204B and FPGA expert may put better comments on this JESD interface related topic. Below is about AD9683 ADC side,

    For the clock to ADC, 200MHz is okay since AD9863 supports a differential clock between 40 MHz and 625 MHz. The required clock input level is differential 0.3 Vp-p to 3.6 Vp-p that is compatible with various logic family inputs such as CMOS, LVDS, and LVPECL. I believe the clock from FPGA would be in one of that logic level. However, please double-check the level on ADC Clock input. If we set reg.0x61 with 0x15 value to run JESD test with user test pattern at the point circled in red below, it is in 10 bit and it is different to user pattern in 8bit. I guess this causes the difference. can you try other test pattern and also at the other test point (scrambler input) ? 

    Thanks

    Tony

  • 0
    •  Analog Employees 
    on Oct 18, 2018 9:55 PM over 2 years ago in reply to THA

    Thanks, Tony, for providing the block diagram above.  You are right about the impact of setting reg 0x61 to 0x15.  When bits 5:4 of the register are set to 01, the test injection point is just prior to the serializer.  This means that there is no transport or link layer operations going on (no data encoding or synchronization (CGS, ILAS) functions).  Its just unscrambled test pattern data.  The FPGA needs to be set accordingly so you're just looking at the raw samples coming out of the deserializer in the XCVRs.