AD9684 decimation ratio

Hi Alex,

Thanks for the reply. 

Could you please give me more information about full bandwidth option?

There is no explanation in datasheet.

Is it possible to have two channels in that mode?

Does ad9684 IP core support that?

The full bandwidth mode of the AD9684 bypasses the DSP and will have 2 channels of 14bit data at 500 MSPS.

Hi Alex,

I use FULL BANDWIDTH mode but still getting decimated by 2. I cannot get decimation by 1.

is there any other specific setup?

I also notice that there is a decimate by 2 block in the chip as default:

how can we turn it off?

Can you please share you current register settings, along with your sample rate? A FFT of the output would also be helpful.

all registers are set to default value (as per your suggestion above) setting 0x200 (chip application mode) to "full bandwidth".

we only have registers:

0x561 (output mode) set to "offset binary"  and 

0x568 (LVDS output mode) set to "parallel interleaved mode (two converters)".

we only need two channels raw data to be sampled no FFT or DSP required.

all registers are set to default value (as per your suggestion above) setting 0x200 (chip application mode) to "full bandwidth".

we only have registers:

0x561 (output mode) set to "offset binary"  and 

0x568 (LVDS output mode) set to "parallel interleaved mode (two converters)".

we only need two channels raw data to be sampled no FFT or DSP required.

What does your output data look like? How do you know that the data is being decimated by 2?

I am using ILA ip core in VIVAdo to check the input and output data of axi-ad9684.

when I probe dc_rawdata_0_s & adc_rawdata_1_s at the output of SERDES module, data is the same every two clocks.

also, when I capture data with the pc, every 32 bits is repeated.