Issues in building ad7616 hdl project for xilinx

axi_hdmi_tx_ip.log

Xilinx Vivado Version: 2019.1

Version of hdl used--------analogdevices/hdl/hdl-hdl_2019_r1

I am trying to build the hdl project for AD7616 for the zedboard zc702 platform.

I am using cygwin to build this project in windows.

The process fails while building the library axi_hdmi_tx . I have attached the generated log. Can anybody help?