I use one AD9208 with my custom board now , in performance test , I find that the performance of the two channels is very different.
1. My configuration, in addition, I additionally turned on the DC offset filt function:
2. Test environment:
1) Use R&S SMU to provide a sampling clock of 3GHz and an input signal of 751MHz. The input signal is passed through a band-pass filter for harmonic suppression (two-stage filter, second harmonic suppression is about 115dB attenuation ), and then a one-to-two power divider is connected to twos channels.
2) The input signal amplitude is about -8dBFs
3) The board schematic design and layout design refer to the official evaluation board
3. Problem description:
SNR (2dB difference) and SFDR (10dB difference) have large differences in the indicators of the two channels of the same chip (invert two input path in test environment also this).
The upper indicator in the figure below is channel 1, and the lower indicator is channel 2.
Ch1: [SNR 60.011 dBFS] [SFDR 67.857dBFS]
Ch2: [SNR 57.891dBFS] [SFDR 78.322dBFS]
Otherwise, I tryed to invert the clk phase for all channels( write reg 0x0109 with 0x1), two channels' SFDR value also inverted, CH1 76dBFS, CH2 became 65dBFS.
Could you plase help me?