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Interfacing with lots of ADCs using LVDS

I need to process up to 24 ADCs, each running at 5-10MSPS. Each ADC needs to have 12 bit resolution, and the ADCs are spread over 3 PCBs. The AD9220ARS would do as a good economical 12bit ADC, but interconnecting 24 of them looks ugly. Quad or octal devices might be a way forward, but has anyone tried using LVDS interfaces to get the sheer number of interconnects down?

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  • Michelle,

    I don't see any processor being able to handle 40 MSPS times 16 channels, which I make to be 640 MSPS - 960 MBytes/sec 7.6 GBits/sec. If on the other hand you are looking at an FPGA to handle the data, both Altera and Xilinx chips have LVDS capability.

    For my project I ended up using dual 14 bit ADCs, with four ADCs connected to each FPGA. Each ADC is connected through a parallel bus, so I needed 56 data pins plus a few clock and phase lines. The buses run at 20 MHz so that I can get the both ADC channels across when sampling at 10 MSPS.

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  • Michelle,

    I don't see any processor being able to handle 40 MSPS times 16 channels, which I make to be 640 MSPS - 960 MBytes/sec 7.6 GBits/sec. If on the other hand you are looking at an FPGA to handle the data, both Altera and Xilinx chips have LVDS capability.

    For my project I ended up using dual 14 bit ADCs, with four ADCs connected to each FPGA. Each ADC is connected through a parallel bus, so I needed 56 data pins plus a few clock and phase lines. The buses run at 20 MHz so that I can get the both ADC channels across when sampling at 10 MSPS.

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