I bought the AD-FMCDAQ2-EBZ board and the KC705 FPGA. I want to stream raw ADC data directly from the ADC to DDR4 RAM in a Ryzen threadripper PC via the PCI express bus using 8 lanes. I have done the Verilog code for streaming data over PCIe but have some problems with the ADC Verilog code that is based on using MicroBlaze and a Linux distribution running at 100 MHz. The PCIe needs to run at 250 MHz using 128 bit wide data to support a sampling frequency of up to 1G samples on two channels.
I managed to figure out the SPI settings by first running the reference design and then replacing the FPGA program with something that could read out the current settings. I thought i could add ILAs to the reference design to be able to read out the input wires to the relevant components, but it won't build. I know that system_util_daq2_xcvr_0, system_rx_0 and system_tx_0 are the relevant Verilog files, but many of the inputs are unclear to me. Especially cfg_beats_per_mutliframe, cfg_octets_per_frame and rx_rate are unclear, but the function of up_cm*, up_es*, up_rx* and up_tx* interfaces also seems unclear.
Is there any documentation for this interface, or is there a simple way to get the settings for the input wires for the AD-FMCDAQ2-EBZ board that doesn't involve writing MicroBlaze code?
