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FMCDAQ2-EBZ input wire settings

I bought the AD-FMCDAQ2-EBZ board and the KC705 FPGA. I want to stream raw ADC data directly from the ADC to DDR4 RAM in a Ryzen threadripper PC via the PCI express bus using 8 lanes. I have done the Verilog code for streaming data over PCIe but have some problems with the ADC Verilog code that is based on using MicroBlaze and a Linux distribution running at 100 MHz. The PCIe needs to run at 250 MHz using 128 bit wide data to support a sampling frequency of up to 1G samples on two channels.

I managed to figure out the SPI settings by first running the reference design and then replacing the FPGA program with something that could read out the current settings. I thought i could add ILAs to the reference design to be able to read out the input wires to the relevant components, but it won't build. I know that system_util_daq2_xcvr_0, system_rx_0 and system_tx_0 are the relevant Verilog files, but many of the inputs are unclear to me. Especially cfg_beats_per_mutliframe, cfg_octets_per_frame and rx_rate are unclear, but the function of up_cm*, up_es*, up_rx* and up_tx* interfaces also seems unclear. 

Is there any documentation for this interface, or is there a simple way to get the settings for the input wires for the AD-FMCDAQ2-EBZ board that doesn't involve writing MicroBlaze code?

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  • Thanks a lot for those additional resuorces. 

    I have figured most of it out now, and I can get the ADC outputs in a buffer in the FPGA. I've tried both with the test patterns and real data.

    I figured out that most of the up interface documentation is in Xilinx GTX document. 

    The only remaining issue I have is that the lanes appear to be misalligned sometimes and then the test patterns will be distorted. There is a lot about LMFC in the ADC document, but I'm still a bit unsure if the reference design actually changes any of these parameters when data alignment is wrong or if I have the wrong timing (I run the ADC at 750M samples per second as that's the maximum rate that can be transferred over PCIe with the KC705). It doesn't appear like the system_rx module can detect this and it happily signals valid data even when it is corrupt. I plan to use test patterns at first, verify those and then turn on real data to make sure I'm not analyzing anything that is corrupted. Any pointers on this would be appreciated.

  • We haven't seen the issue in our tests, but we are using the 1GSPS sampling. 

    If using linux, there is a jesd_status application( which reads the status of the links and the lane latency. At this point the JESD204 IP doesn't detect runtime misalignment errors.