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ad9226: single ended measuring span is 0.1v when vref=1v

I am starting to use this ADC and would be glad if someone help me with following problem:

When I connect SENSE pin to VREF and VINB, VREF-VREF/2 to VREF+VREF/2 span is expected at VINA input pin. But I am getting OTR signal for VINA = VREF-0.05v and VREF+0.05v instead. (VREF pin output voltage is 1v). Bit values are 0x000 at 0.95v and 0xfff at 1.05v. although Mode pin is connected to 5v, I observe jump in output bits value around 1v input.

When I connect SENSE to GND, vref is 2v, things look better, measuring span looks correct (vref-vref/2 to vref+vref/2), but still observing jumping in output 12bit value around VINA=vref, and is not linearly increasing when sweeping voltage on VINA input.

I am using 3.3v clocks on clock input (tried 1mhz,10mhz and 60mhz). Maybe part is working incorrect with 3.3v clock s and require 5v clock signal?

Using single-ended configuration from datasheet with internal reference, internal reference also connected to VINB.

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  • It turns out that problem occurs only when MODE pin is set to 5v (clock stabilizer on).

    If MODE pin is left open, results are good.

    Please comment.

  • Hello,


    It sounds it was tried to set Vref at 1V and 2V by configuring SENSE pin and there is an issue only when Mode pin is tied to 5V case(Binary Data Format, Clock Stabilizer on). What you observed at the digital data and OTR signal are not what expected. For better understanding on the issue, may I get some additional information?

    1. Is it on AD9226 Evaluation Board or AD9226 on your system?

    2. Does the connection looks like below (for Vref=1V case) @ Mode =5V ? May I get the schematic for AD9226 on your schematic(please send it to tony.ha@analog.com if you want to email it )   What are AVDD and DRVDD?  What is the voltage on VINB?

    3. 3.3V Clock

        3.3V logic level for Clock is okay as you can see the requirement at the " Logic Inputs" section in Digital Spec table(page 3). You said, you tried Clock input at 1mhz, 10mhz and 60mhz. Are they mhz or MHz?

    4. Digital data and OTR @ Mode=GND (for Data format at 2's complement, Clock stabilizer Enabled)

         Can you check if digital data and OTR work as expected while Mode pin (assuming you are using AD9226 in SSOP package) is set to GND?

    Thanks

    Tony

  • 1. it is on my board

    2.

    On my schematic there is resistive divider, but i tried all cases SENSE connected to GND, SENSE connected to VREF. AD603 is on the schematic, but it is not soldered / no connection.

    DRVDD,VDD = 5V. Vref is connected to VINB through 33ohm resistor, and measured as expected.

    3. Clock is in  MHz (mega)

    4. I will try to connect MODE to GND and provide results later.

    yes, i use AD9226 in ssop package

    p.s.: 5v network highlighted:

Reply
  • 1. it is on my board

    2.

    On my schematic there is resistive divider, but i tried all cases SENSE connected to GND, SENSE connected to VREF. AD603 is on the schematic, but it is not soldered / no connection.

    DRVDD,VDD = 5V. Vref is connected to VINB through 33ohm resistor, and measured as expected.

    3. Clock is in  MHz (mega)

    4. I will try to connect MODE to GND and provide results later.

    yes, i use AD9226 in ssop package

    p.s.: 5v network highlighted:

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