ad9226: single ended measuring span is 0.1v when vref=1v

It turns out that problem occurs only when MODE pin is set to 5v (clock stabilizer on).

If MODE pin is left open, results are good.

Please comment.

It turns out that problem occurs only when MODE pin is set to 5v (clock stabilizer on).

If MODE pin is left open, results are good.

Please comment.

Hello,

It sounds it was tried to set Vref at 1V and 2V by configuring SENSE pin and there is an issue only when Mode pin is tied to 5V case(Binary Data Format, Clock Stabilizer on). What you observed at the digital data and OTR signal are not what expected. For better understanding on the issue, may I get some additional information?

1. Is it on AD9226 Evaluation Board or AD9226 on your system?

2. Does the connection looks like below (for Vref=1V case) @ Mode =5V ? May I get the schematic for AD9226 on your schematic(please send it to tony.ha@analog.com if you want to email it )   What are AVDD and DRVDD?  What is the voltage on VINB?

3. 3.3V Clock

    3.3V logic level for Clock is okay as you can see the requirement at the " Logic Inputs" section in Digital Spec table(page 3). You said, you tried Clock input at 1mhz, 10mhz and 60mhz. Are they mhz or MHz?

4. Digital data and OTR @ Mode=GND (for Data format at 2's complement, Clock stabilizer Enabled)

     Can you check if digital data and OTR work as expected while Mode pin (assuming you are using AD9226 in SSOP package) is set to GND?

Thanks

Tony

1. it is on my board

2.

On my schematic there is resistive divider, but i tried all cases SENSE connected to GND, SENSE connected to VREF. AD603 is on the schematic, but it is not soldered / no connection.

DRVDD,VDD = 5V. Vref is connected to VINB through 33ohm resistor, and measured as expected.

3. Clock is in  MHz (mega)

4. I will try to connect MODE to GND and provide results later.

yes, i use AD9226 in ssop package

p.s.: 5v network highlighted:

THA said:

 Can you check if digital data and OTR work as expected while Mode pin (assuming you are using AD9226 in SSOP package) is set to GND?

When I connect mode to GND, there is a similar problem, but input signal is totally disappears.

mode pin not connected: work as expected, input signal is clearly visible (in my test app on PC)

mode pin to 5v: very smal measuring span, strange scale (signal rapidly changes near VREF and goes out of range - OTR)

mode pin to GND: output does not change (bits are stuck in position MSB-> 000001010100 <-LSB). Although I do not apply full-range signal. Currently I apply small amplitude test signal centered around VREF, but it is clrearly visible with mode pin floating. It is distorted when VREF is 5V and it is does not change when VREF is gnd.

Dear Tony, I've send you a photo of my PCB board on December 7th.

Any Idea why my setup is working only with "Mode" pin leaved unconnected?

Hello Georgy,

First, I want to make sure the AVDD Supply Voltage. You showed 5V Network in blue line. However, there is no supply connection to AVDD on the schematic.

The schematic also says that your circuit is at resistor programmable reference configuration. So Vref is set externally that is about 1.6V in calculation(Vref=1V x (1+2.4K/3.9K), not sure how much R5 33ohm impact on the voltage at VINB and VREF Pin .

So can you double-check the voltage at AVDD Pin and VREF,VINB pins?

What is D3,D4,D5 and U13,U39? Do you tie Analog Inputs to other devices?  

Here is what to try :

- Make sure AVDD pins(Pin 15 and Pin26) are at 5V.

- Tie Mode pin to AVDD at 5V

- take R4 and R3 out --> That makes Vref=1V, common-mode voltage 1V , VINA can be in 0.5~1.5V range(like Figure 5a)

- check how it works ?

If it doesn't work, we need to look at the analog input connections to other devices assuming it is connected to U13 and U39.

Thanks

Tony  

1. 5V pins highlighted in blue: 28_DRVDD 26_AVDD 22_MODE 15_AVDD

2. MODE pin was tied in first prototype board (shown on image above)

3. I will try this later:

"take R4 and R3 out --> That makes Vref=1V, common-mode voltage 1V , VINA can be in 0.5~1.5V range(like Figure 5a)"

4. D3,D4,D5 and U13,U39 are solder jumpers (D) and connectors(U). Wrong letter

5.

"The schematic also says that your circuit is at resistor programmable reference configuration. So Vref is set externally that is about 1.6V in calculation(Vref=1V x (1+2.4K/3.9K), not sure how much R5 33ohm impact on the voltage at VINB and VREF Pin ."

I use internal reference:

I have made a new layout using following example (exact copy of schematic shown on image, with 33 ohm connecting VINB and VREF), still experiencing the same problem with clock stabilizer.

1) MODE pin open: works
2) MODE to 5V: not working properly, distorted signal
3) MODE to GND: not working properly zero signal

I have noticed that CLK input of AD9226 pulls my 20MHz  3.3Vpp MCU clock output to 4Vpp.

Also when mode pin is connected to 5V/GND, CAPB and CAPT voltage rises/drops, while VREF remains normal:

1) MODE pin open: CAPB=2.04V CAPT=3.08V (VREF=1.04V)
2) MODE pin to 5V: CAPB=3.72V CAPT=4.72V (VREF=1.04V)
3) MODE pin to GND: CAPB=0V CAPT=1.2V   (VREF=1.04V)

I am using oscilloscope and computer to compare AD9226 VINA input signal to AD9226 digitized data to ensure there are no problem with input signal on VINA pin.