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Direct Digital Synthesis (DDS)
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Documents AD9910 frequency update rate
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    • AD9910 and AD9912: Residual Phase Noise Definition and Measurement
    • AD9910 Evaluation board driver for Win7
    • AD9910 frequency update rate
    • AD9910: EVB R43 resistor value
    • AD9910: output circuit clarification
    • AD9910: output filter design
    • AD9910: Programming through SPI-Interface
    • AD9910: REFCLK termination
    • AD9910: REFCLK termination 2
    • AD9910EVB_Filter Question
    • AD9910_Multichip SYNCHRONIZATION.
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  • +AD9912: FAQ
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AD9910 frequency update rate

Q 

I am hoping to use one of your DDS devices as a chirp generator in a radar
system I am currently developing.

1) Am I correct in assuming that the AD9910 will allow me to generate a linear
frequency ramp with a frequency step time interval / update rate of 4nS ?

2) Does the AD9910 offer the fastest frequency update rate in your DDS range or
is there a faster device available ?

3) Do you have a road map which details how the frequency update rates of your
DDS devices are likely to increase in the future ?

 

A 

1) Am I correct in assuming that the AD9910 will allow me to generate a linear
frequency ramp with a frequency step time interval / update rate of 4nS ?
->Yes. The fastest frequency step time interval setting is equal to the
SYNC_CLK rate. The SYNC_CLK rate = system clock / 4. So, if the system clock is
1GHz then the period of the SYNC_CLLK is 4ns.

2) Does the AD9910 offer the fastest frequency update rate in your DDS range or
is there a faster device available ?
->If the DRG is the source of the frequency ramp, then yes the AD9910 provides
the fastest frequency step time interval setting.
However, if the frequency tuning word is provided externally on the fly for
whatever reason, the AD9915 has a full 32-bit BUS which provides a faster way
to update the 32-BIT FTW faster. In that case,
The update rate is also the SYNC_CLK rate. In that part, the SYNC_CLK is system
clock/ 16. So, if the system clock is 2.5GHz then the period of the SYNC_CLLK
is  approximately 7ns. The AD9910 cannot update the full 32-bit FTW faster than
that.

3) Do you have a road map which details how the frequency update rates of your
DDS devices are likely to increase in the future ?
->TBD

Tags: ad9910
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