Question 1

Are any of your DDS products space qualified?

Accepted Answer

Q. 
 Are any of your DDS products space qualified? 
 
 -------------- 
 
 A. 
 No.

Question 2

Are there any specific recommendations regarding via fill material in the circuit board for the thermally enhanced package styles associated with some ADI DDSs?

Accepted Answer

Q. 
 Are there any specific recommendations regarding via fill material in the circuit board for the thermally enhanced package styles associated with some ADI DDSs? 
 
 ------------------- 
 
 A. 
 The vias must be through-plated with solder as the fill material (solder is much less expensive than silver-over-copper plate).

Question 3

DDS Tutorial - Introduction to DDS

Accepted Answer

This Direct Digital Synthesis tutorial with audio provides a description of the three fundamental elements of a direct digital synthesizer (DDS). Use the play button to start the presentation and advance to the next slide. For more instructions, see the DDS Tutorial User Guide .

Question 4

DDS Tutorial - SINC Envelope Correction

Accepted Answer

This Direct Digital Synthesis tutorial with audio describes correcting for the DAC's sin(x)/x (or sinc) response. Use the play button to start the presentation and advance to the next slide. For more instructions, see the DDS Tutorial User Guide .

Question 5

DDS Tutorial - The Accumulator

Accepted Answer

This Direct Digital Synthesis tutorial with audio describes the function of the accumulator, the first DDS element. Use the play button to start the presentation and advance to the next slide. For more instructions, see the DDS Tutorial User Guide .

Question 6

DDS Tutorial - The Angle-to-Amplitude Converter

Accepted Answer

This Direct Digital Synthesis tutorial with audio describes the function of the angle-to-amplitude converter, the second DDS element. Use the play button to start the presentation and advance to the next slide. For more instructions, see the DDS Tutorial User Guide .

Question 7

DDS Tutorial - The DAC

Accepted Answer

This Direct Digital Synthesis tutorial with audio describes the function of the analog-to-digital converter (DAC), the third DDS element. Use the play button to start the presentation and advance to the next slide. For more instructions, see the DDS Tutorial User Guide .

Question 8

DDS Tutorial - The DAC Reconstruction Filter

Accepted Answer

This Direct Digital Synthesis tutorial with audio describes the function of the DAC reconstruction filter and provides a description of four types of analog filters. Use the play button to start the presentation and advance to the next slide. For more instructions, see the DDS Tutorial User Guide .

Question 9

DDS Tutorial - The DDS in Action

Accepted Answer

This Direct Digital Synthesis tutorial with audio shows an animated presentation of the DDS elements in action. Use the play button to start the presentation and advance to the next slide. Use the play button to start the presentation and advance to the next slide. For more instructions, see the DDS Tutorial User Guide .

Question 10

DDS Tutorial - User Guide

Accepted Answer

This presentation with audio provides instructions for using the presentation tool for the Direct Digital Synthesis (DDS) Tutorial Series. Use the play button to start the presentation and advance to the next slide. 
 PLEASE NOTE: This content is best viewed in Internet Explorer and may not be Chrome compatible. 
 &amp;#160; 
 Here are links to the various modules in the Direct Digital Synthesis (DDS) Tutorial Series: 
 Introduction to DDS 
 The Accumulator 
 The Angle-to-Amplitude Converter 
 The DAC 
 The DAC Reconstruction Filter 
 SINC Envelope Correction 
 The DDS in Action

Question 11

Do you recommend a linear or switching power supply?

Accepted Answer

Q: 
 Do you recommend a linear or switching power supply to power the DDS? 
 A: 
 In the past, a linear supply was greatly preferred over a switching supply because of the presence of switching transients on the dc output of the switchers. Switching supplies have made great improvements in terms of switching noise suppression over the past years. The most important consideration is adequate power supply bypassing directly at the device pins. On a side note, if you suspect a spur from a switching supply see AN-927.

Question 12

How does the REF CLK performance affect the DDS output performance?

Accepted Answer

Q. 
 How does the REF CLK performance affect the DDS output performance? 
 ---------------------------------------------------------------------------------------------------------------- 
 A. 
 The DDS is basically a high resolution sine source frequency divider. Frequency drift, timing jitter, or excessive phase noise associated with the REF CLK source will transfer to the DDS output. Therefore, the REF CLK performance can limit the DDS performance.

Question 13

Is there a relationship between the sample rate and the maximum update rate?

Accepted Answer

Q. 
 Is there a relationship between the sample rate and the maximum update rate? 
 -------------------------------------------------------------------------------------------------------------------------- 
 A. 
 Yes, there is. In a basic DDS, it is possible to update your tuning words every clock cycle. As DDS rates have increased, though, ADI determined that interleaving multiple lower speed DDS cores to mimic a higher speed DDS core was more power efficient. The simplest interleave would have two DDS cores and have the DDS output toggle between those two engines to effectively double the sample rate. In order to keep the power consumption more manageable we have interleaved more and more cores to push to higher rates. 
 As of early 2011, the top DDS speed was 1.0 GHz (AD9858, AD9910, AD9912). These devices feature DDS cores with 4 (AD9912) or 8 (AD9858, AD9910) slower, interleaved cores. The DDS engine, as a whole, streams through the interleaved engines to establish the 1 GSPS rate. To prevent glitches and avoid miscalculations in the digital domain, it is important to restrict updates of the tuning words to the point in time where the DDS engine block reverts back to the initial interleaved core, rather than allowing an update to initiate at any point in the interleave process. This means that for a 1 GSPS DDS with an interlave factor of 8, the actual re-programming requires at least 8 ns between frequency/phase/amplitude changes

Question 14

Learning more about Direct Digital Synthesis Technology (DDS)

Accepted Answer

Q. 
 I have heard DDS is an alternative to Phase Locked Loops (PLLs) for frequency synthesis, but I am not familiar with Direct Digital Synthesis Technology. Does ADI offer any training or tutorial material that I can use to learn more about DDS? 
 -------------------------------------------------------------- 
 A. 
 Yes, ADI offers a Direct Digital Synthesis (DDS) Tutorial Series. This series consists of slide modules with an accompanying voice-over. Links to the modules in this series are included below: 
 Direct Digital Synthesis (DDS) Tutorial Series 
 FAQ: DDS Tutorial - User Guide 
 Introduction to DDS 
 The Accumulator 
 The Angle-to-Amplitude Converter 
 The DAC 
 The DAC Reconstruction Filter 
 SINC Envelope Correction 
 The DDS in Action 
 These modules are relatively high level, more mid-level depth modules may be developed depending upon the response to these.

Question 15

Why would I choose to use DDS for synthesizing a signal rather than a PLL?

Accepted Answer

Q. 
 Why would I choose to use DDS for synthesizing a signal rather than a PLL? 
 ----------------------------------------------------------------------------------------------------------------------------- 
 A. 
 Let me start with a basic comparison between the two, but keep in mind this can change over time. 
 In general, it is fair to say that DDS technology provides some specific advantages: dynamic frequency and phase control is relatively easy, and is not prone to ringing or settling, so if you need to do any sweeping or hopping, DDS is a good option to start. DDS also provides much finer tuning resolution than even a fractional N PLL can provide. The digital nature of the DDS also makes digital synthesis more repeatable. 
 Conversely PLL technology offers other benefits: Generally speaking it is less expensive and less power hungry than DDS technology. Perhaps most importantly, you have the ability to 'upconvert' your input frequency, whereas with the DDS is a Nyquist system, and limited to providing outputs that are <50% of the sampling clock frequency that is used. 
 But if you look beyond the surface, you 'll find a whole lot of softening of these boundaries. For example: There exist both 'ping pong' and 'fast hopping' PLLs on the market (including products from ADI) which close the gap in terms of their ability to provide frequency and even phase agile outputs. Fractional N PLLs help close the gap on timing resolution for that matter. Conversely, ADI has also closed the gap for DDS products in some cases. Specifically worth noting is the AD9913, which significantly closes the gap both in power and in cost to PLLs. ADI's DDS portfolio includes many products with reference clock PLLs on board, allowing customers to upconvert their reference clock before dividing down through the DDS, meaning the output can now be a higher frequency than the reference - note is is also possible to bandpass filter a DDS output isolating a Super Nyquist image to obtain an output frequency that is higher than the reference frequency source provided. 
 And taking it a step further, where fractional N PLLs closed the gap in terms of frequency granularity, the Programmable Modulus mode implemented in the AD9913 (and eventually most future DDS devices), widens that gap back up.

Question 16

What are the basic things to be checked when using the DDS evaluation board via external control?

Accepted Answer

Q: Most of the DDS evaluation board comes with input/output headers for ease of accessibility to some digital input/output pins of the DDS. If I want to use these pins for external control, what are the basic things to be checked? 
 A: Most of the DDS evaluation board has available input/output headers that correspond to some of the digital input/output pins of the DDS. To name the DDSs of which their evaluation boards has this availability are the following:

AD985x 
 AD995x 
 AD991x

Most customers access these pins but problems arise due to incorrect handling of these pins. This will serve as a guideline on what the customers will check when using the output pins and/or input pins. 
 Output Pins 
 Some DDS output pins are provided for ease of access when the user wants to monitor the output of that pin. Or, it can be used to interface with external circuitry. These pins can be used directly without having to configure the logic state of other pins. Some of these typical pins may vary on each DDS board: 
 
 SYNC_CLK 
 SDO 
 DROVER 
 PLL_LOCK 
 
 Input Pins 
 Some DDS digital input pins through the I/O headers are provided to give the customers option in controlling the DDS. The default of the evaluation board is being set-up to be controlled by the corresponding DDS evaluation software. However, a partial or complete external control to the evaluation board can be done too. Some of these typical pins are the following and may vary on each DDS board: 
 
 MASTER_RESET 
 EXT_POWER_DOWN 
 SCLK 
 SDI 
 CSB 
 I/O_UPDATE 
 PROFILE PINS 
 FUNCTION PINS 
 PARALLEL PORT PINS 
 
 Partial External Control 
 This is the set-up in which the evaluation board is first controlled using the ADI software, before shifting to external control on the DUT. The basic things to be checked are the following: 
 
 Set-up the evaluation board so that it is controlled by the ADI software. The user may refer to the DDS Evaluation Board User&rsquo;s Guide. 
 After the DDS registers is programmed using the evaluation software, the user may now proceed to control the DUT externally. 
 Locate the Master_Reset or simply Reset pin and set to logic 0 so as not to lose the DUT register settings. 
 Make sure the EXT_POWER_DOWN pin is set to logic 0. 
 Most of the DDS evaluation boards have logic buffers between the USB interface and the DDS. There are jumpers that enable/disable these logic buffers. Locate for these jumpers and set to disable to tri-state the ICs on the evaluation board. The user may refer to the evaluation board schematic to easily identify these jumpers. 
 Selecting the profile mode can be done two ways: hardwire each profile pin to logic 1 or 0, or connect interface cable from these pins to control it externally. 
 Connect ALL the required input pins to the external circuitry via interface cable to control the DUT. 
 Set the Function Pins (applicable only to AD9914/AD9915) to the desired parallel-port configuration. 
 
 Complete External Control 
 This is the set-up in which the evaluation board is 100% to be controlled externally. The basic things to be checked are the following: 
 
 Most of the DDS evaluation boards have logic buffers between the USB interface and the DDS. There are jumpers that enable/disable these logic buffers. Locate for these jumpers and set to disable to tri-state the ICs on the evaluation board. The user may refer to the evaluation board schematic to easily identify these jumpers. 
 Connect ALL the required input pins to the external circuitry via interface cable to control the DUT. Some critical inputs are the Master_Reset and the external power down pins. 
 Selecting the profile mode can be done two ways: hardwire each profile pin to logic 1 or 0, or connect interface cable from these pins to control it externally. 
 Set the Function Pins (applicable only to AD9914/AD9915) to the desired parallel-port configuration. 
 Apply power, reference clock and control ALL digital inputs. When controlling the digital inputs, make sure that there is a defined logic state for each input. The external power down must be set to logic 0 to ensure the DDS is not in power-down mode. 
 Send Master Reset to the DUT. This places the DDS to a known state. 
 Program the registers to the desired configuration. 
 
 May it be partial or complete external control, make sure to apply power that is within specification. The reference clock must also be referred to the datasheet for specification. Some DDS has XTAL_SEL or REF_SELECT pin that is tied low or high depending if crystal or external clock is the source of clock input. Whether the external control is using serial or parallel communication, issuing an I/O_UPDATE is always necessary when programming the registers.

Question 17

Is it okay to use a frequency modulated (FM) source as my clock input to the system clock of the DDS?

Accepted Answer

Q: Is it okay to use a frequency modulated (FM) source as my clock input to the system clock of the DDS 
 A: No. 
 Typically, the DDS system clock is the timing source for much of the internal workings of the DDS. A system clock with FM can introduce excessive jitter. Too much jitter will cause timing problems within the DDS device and significantly degrade performance. This is applicable to both PLL disabled and PLL enabled. Thus, the clock source must be a stable single-tone frequency source.

Question 18

What’s the function of the SYNC_CLK pin on the DDS?

Accepted Answer

A: What&rsquo;s the function of the SYNC_CLK pin on the DDS? 
 Q: The SYNC_CLK pin is provided so the user can externally synchronize the IO_UPDATE signal and/or profile pin signals to the internal timing of the DDS core. For example, if the frequency tuning word is being continuously updated via SPI operations and consistent propagation time through the device is desired, then the IO_UPDATE must be sent synchronously to the SYNC_CLK. In addition, if multiple DDS devices are to be synchronized, a common IO_UPDATE to all parts must be synchronized to the master SYNC_CLK device. 
 If the IO_UPDATE signal on the IO_UPDATE pin is asynchronous to the SYNC_CLK, the pipe line delay through the device will incur an uncertainty of +/- one SYNC_CLK period. Note, the minimum pulse width of IO_UPDATE signal must be at least one SYNC_CLK period to be registered. 
 If more than one profile pin is switched at a time, the profile signals are required to be synchronized to the SYNC_CLK. If not, the correct internal profile register may or may not be chosen. However, if only one profile pin is switched at a time, the profile signal can be sent asynchronous to the SYNC_CLK, but the same pipe line delay uncertainty of +/- one SYNC_CLK period will exist. 
 Note in most DDS products, if the profile signals are sent asynchronous to the SYNC_CLK and the wrong profile is selected, issuing an IO_UPDATE can force the correct profile setting. However, the output would have been at the wrong profile setting until the correct profile setting is forced.

Question 19

Where can I find in the datasheet on how the output of the DDS will drift?

Accepted Answer

Q: Where can I find in the datasheet on how the output of the DDS will drift? 
 A: The quantitative value on how the output of the DDS will drift is not found in the DDS datasheet. 
 Frequency drift is an arbitrary offset of a clock source from its nominal frequency. The DDS output is ultimately related to the purity of the clock source used as the system clock of the DDS. That means, if the frequency of the clock source drifts, the output of the DDS will also drift. Thus, the stability of the DDS output depends on how stable the clock source is. 
 
 The following table summarizes the best stability each type of oscillator can hold based on today&rsquo;s manufacturing process:

Temperature

XO

TCXO

OCXO

0&deg;C to 70&deg;C

&plusmn;10 ppm

&plusmn;0.5 ppm

&plusmn;0.003 ppm

-20&deg;C to 70&deg;C

&plusmn;25 ppm

&plusmn;0.5 ppm

&plusmn;0.003 ppm

-40&deg;C to 85&deg;C

&plusmn;30 ppm

&plusmn;1 ppm

&plusmn;0.02 ppm

-55&deg;C to 125&deg;C

&plusmn;50 ppm

N/A

For example, if TCXO is used as the clock source (drift is 0.0001% or +/-1ppm), you are likely to see frequency drift in the 1ppm range at the DDS output. 
 This FAQ was generated from the following discussion: Does the output frequency of a DDS drift?

Question 20

Why does a DDS need a reconstruction filter?

Accepted Answer

Q: Why does a DDS need a reconstruction filter? 
 A: ADI&rsquo;s DDSs include an integrated DAC, which converts the &ldquo;numerical&rdquo; sinusoid produced by the DDS to an analog sinusoid waveform like that in Figure 1. 
 
 Figure 1 
 This picture is an example of the DAC output signal when the DDS is generating a relatively high output frequency (approximately 1/18 th of the sample DAC sample rate). This clearly illustrates the sampled nature of the DAC output. The sampled nature of the DAC output as shown in Figure 1 is the primary reason for the need of a reconstruction filter. The time domain signal in Figure 1 appears in the frequency domain like Figure 2. 
 Figure 2 
 
 In Figure 2, fc is the sampling frequency (i.e., the DDS clock frequency). The vertical black line at approximately 0.1fc represents the magnitude of the output frequency of the DDS. The vertical red lines represent the images of the fundamental, which are a consequence of sampled DDS output. Notice that there is a roll off at the frequency response of the signal before 0.5fc and the images are located beyond 0.5fc. So the role of the reconstruction filter is to significantly attenuate the images while preserving the fundamental. The result is near perfect &ldquo;reconstruction&rdquo; of the sinusoid signal. 
 This FAQ was generated from the following discussion: Why does a DDS need a reconstruction filter?

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DDS: FAQ