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AD9912 Register settings

Having the AD9912 with a SI5351 at 25Mhz/670mV/pp as input for the DDS.

The communication is working ok (I guess) I have a start frequence S4-S1 (0,1,0,0)

so I get the 77,75879Mhz. After a software 1-time run of updating the registers the frequency changes

to +/- 85,560Mhz. Here after doing a FTW programming, but no frequency is changed.

Do I need something to do with S4-S1 after startup? Or do I have my registers not good?

The datasheet is a bit unclear in my vision about this and setting multipliers.

/////////////////////////////////////////////////////
//                                                 //
// Power-down & enable                             //
// Register 0x0010 default 0xC0 or 0xD0 [2]        //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Powerdown_digital      = 0;       // bit 0
  uint8_t Powerdown_full         = 0;       // bit 1
  uint8_t Not_used_1             = 0;       // bit 2
  uint8_t Not_used_2             = 0;       // bit 3
  uint8_t Powerdown_sysclock_pll = 0;       // bit 4*
  uint8_t Enable_output_doubler  = 0;       // bit 5*
  uint8_t Enable_CMOS            = 0;       // bit 6*
  uint8_t Powerdown_HSTL         = 1;       // bit 7

/////////////////////////////////////////////////////
//                                                 //
// Register 0x0012 default 0x00 [3]                //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Reset_DDS              = 0;       // bit 0

/////////////////////////////////////////////////////
//                                                 //
// Power-down & reset                              //
// Register 0x0013 default 0x00 [4]                //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Not_used_3             = 0;       // bit 0
  uint8_t Reset_sdivider         = 0;       // bit 1
  uint8_t Not_used_4             = 0;       // bit 2
  uint8_t Reset_sdivider2        = 0;       // bit 3
  uint8_t Not_used_5             = 0;       // bit 4
  uint8_t Not_used_6             = 0;       // bit 5
  uint8_t Not_used_7             = 0;       // bit 6
  uint8_t Powerdown_fund_DDS     = 0;       // bit 7

/////////////////////////////////////////////////////
//                                                 //
// System clock N-divider                          //
// Register 0x0020 default 0x12 [5]                //
// 25Mhz = 20                                      //
/////////////////////////////////////////////////////

  uint8_t N_divider0             = 0;       // bit 0*
  uint8_t N_divider1             = 0;       // bit 1*
  uint8_t N_divider2             = 1;       // bit 2*
  uint8_t N_divider3             = 0;       // bit 3*
  uint8_t N_divider4             = 1;       // bit 4*
  uint8_t Not_used_8             = 0;       // bit 5
  uint8_t Not_used_9             = 0;       // bit 6
  uint8_t Not_used_10            = 0;       // bit 7

/////////////////////////////////////////////////////
//                                                 //
// PLL parameters                                  //
// Register 0x0022 default 0x04 [6]                //
//                                                 //
/////////////////////////////////////////////////////

  uint8_t Charge_pump1           = 0;       // bit 0*
  uint8_t Charge_pump2           = 0;       // bit 1*
  uint8_t VCO_range              = 1;       // bit 2
  uint8_t Reference_2x           = 0;       // bit 3*
  uint8_t Not_used_11            = 0;       // bit 4
  uint8_t Not_used_12            = 0;       // bit 5
  uint8_t Not_used_13            = 0;       // bit 6
  uint8_t VCO_autorange          = 0;       // bit 7

  • You may be missing something, as I did not see any mention of the IO_UPDATE pin in your post.

    Note there are two stages associated with the programming registers. The first stage comprises the SPI registers. The second stage comprises the BUFFER registers. It is the BUFFER registers that actually control the internal device functions. When you program the SPI registers the internal device functions remain unchanged until you provide a Logic 0 to 1 transition on the IO_UPDATE pin. Doing so transfers the contents of the SPI registers to the BUFFER registers and activates the corresponding device functions (the frequency tuning word, for example).

  • Here is the I/O update. I can change the register data and all signals

    are running smoothly through a level shifter.

    void SendREGISTERdata() {

      PORTB &= ~(1<<PORTB2); // SS

      SPDR = Instruction_header_register >> 8;
      WAIT;

      SPDR = Instruction_header_register;
      WAIT;

      SPDR = Register_data[z];
      WAIT;

      PORTB |= (1<<PORTB1); // I/O
      PORTB &= ~(1<<PORTB1); // I/O

      PORTB |= (1<<PORTB2); // SS

    }

    As I earlier mentioned by myself is that the V(il) is not exactly 0,0V or less then 0,8V. Maybe in a long run with 8 bytes it can perhaps give a problem.

  • The timing of the various signals looks OK. However, if the voltage levels are not low enough to properly signify Logic 0, this could be a problem.

    Have you tried to read back a register after writing to it?

    If you can write and then read back a register it will at least prove you can program the registers as intended.

  • Well, it is somekind of working. It seems a problem in programming

    the registers. I have change the "bytes to transfer" from streaming to 3 bytes.

    So now I know the DDS is working I need to find out why I cannot send 8 bytes

    of data in streaming mode.