AD9914 External SPI Control – Write Works but Readback Issue

Hi  ada533 ,

Let me answer your questions below:

1. In 2 wire mode, SDIO is bidirectional and SDO is high impedance. Data is always written on SDIO, but for a readback operation the AD9914 drives SDIO during the readback phase and tri-states it otherwise. 

2‑wire SDIO register read sequence. Assuming default 2‑wire mode (CFR1 bit 1 = 0):

1. Idle/setup
   • CSB high (inactive).
   • SCLK at its idle level per your SPI mode.
   • SDIO configured as output from your controller.
2. Instruction phase
   • Drive CSB low.
   • Clock out the 8‑bit instruction/address byte on SDIO with SCLK:
     • MSB‑first by default (CFR1 bit 0 = 0). 
     • Instruction encodes a READ of the target register.
3. Turnaround at end of instruction
   • After the last instruction bit is clocked.
     • Keep CSB low.
     • Immediately reconfigure SDIO as input/high‑Z (stop driving it)
   • The datasheet notes that any SCLK stall between instruction and data phases is not required; you can proceed directly to data clocks. 
4. Data phase (32‑bit readback for CFR1)
   • Continue generating SCLK edges within the specified read‑cycle frequency limit. 
   • The AD9914 now drives SDIO with the register contents during the read operation; otherwise SDIO is tri‑state. 
   • Sample SDIO on the appropriate edge per your SPI mode for 32 bits of data.
5. End of transaction
   • After all data bits are received, deassert CSB high.
   • SDIO returns to tri‑state once CSB is high.

2. Release SDIO after the falling/rising edge (per your SPI mode) that clocks out the last instruction/address bit and before the next clock edge used for data readback. The controller must not continue driving SDIO once the instruction phase is complete.

3. No. The AD9914 does not require any extra turnaround clock and delay between the instruction phase and the 32-bit read data phase. The datasheet explicitly states that the SCLK stall shown between the instruction byte and data transfer in the timing diagrams is not required. You can begin clocking the data phase immediately on the next SCLK edges after the instruction byte, with SDIO released to input (2-wire) or data appearing on SDO (3-wire).

4. I am not knowledgeable how AXI Quad SPI + Xilinx XSpi_Transfer() works or have never used it anyway. I cannot share anything with regards to the mentioned component. 

5. For the AD9914, the device powers up in the default 2-wire (bidirectional SDIO) serial mode. To move to 3-wire mode (separate SDIO input and SDO output), the usual approach is:

1. Communicate initially using the default 2-wire SDIO interface.
2. Write CFR1 and set the SDO active bit (CFR1[1] = 1).
3. Pulse IO_UPDATE so the new CFR1 value becomes active.
4. After the update, use:
   • SDIO (Pin 20) as input-only to the AD9914.
   • SDO (Pin 19) as the dedicated readback output.

6. No, neither SYNCIO nor a special ResetSPI operation is normally required before the first external SPI transaction. A hardware RESET after power-up, a valid reference clock, and proper serial-mode pin configuration are the key requirements.

7. Yes, a valid REF_CLK is required, 

All the best,

Jules

My aim: 2 wire mode should be changed to 3 wire mode so that i could use separate data lines for writing and reading data. 

Q1: I have given Ref Clk of 500 MHz with input power of 0 dBm from Signal Generator but how to check whether SYNC CLK is produced or not?

Q2: And i have connected the SYNC_IO-Buf Pin to GND pin(P101A header) present in AD9914 Eval board. Is this correct or i should toggle it? 

Q3:Currently i am doing Toggling of Master reset,then doing write data,then toggling IO Update Pin and then Read data,is this correct or not?

Q4: are there any additional jumper settings or default data in the any register to be changed or checked for the SPI write/Read to work?

Regards.

ada533

Hi ada533 ,

1. You can check J100 if you're seeing signals in SYNC_CLK. There's also a bit that you can enable/disable on CFR2[11].

2. SYNC_IO tied to GND: Acceptable. SYNC_IO is an optional synchronous-reset for the serial port state machine; it's active-high and only needed to recover from a desynchronized SPI frame. Holding it low permanently is fine. If you ever lose sync, pulse it high (≥1 SYNC_CLK cycle) rather than leaving it floating.

3. Sequence: Correct, with two additions:

• Master Reset: pulse high then low, and wait ≥ a few SYNC_CLK cycles before the first SPI access
•  A read does not require IO_UPDATE — IO_UPDATE only transfers the serial-port buffer into the active internal registers. Reads come from the buffer, so read-back verifies the write even before IO_UPDATE. So: MRESET → write → read back (verify SPI) → IO_UPDATE (apply).
• Make sure CS is deasserted between each instruction/data frame; the frame is instruction byte (bit7 = R/W, bits[6:0] = address) followed by the data bytes, MSB-first, on SDIO sampled on rising SCLK.

4. Jumpers / register defaults to check:
• Set the board to external/serial control, not the on-board USB controller — if the EVB's microcontroller is driving SCLK/SDIO/CS, it will contend with your host. Remove/disable those jumpers (or don't power the USB interface).

All the best,

Jules